Clock Distribution and Balancing Methodology for a Large and Complex ASIC Design

Abstract
The paper describes a clock distribution and balancing methodology for a high performance and low power ASIC design. Various issues were discussed and solutions were provided based on our experience in a low power 3G wireless application platform ASIC design. The paper focuses on critical topics such as clock phase delays & skew reduction, maximization of clock gating effects, operation mode dependent clock delay variation control, clock signal integrity assurance, and clock balance automation strategy development. The presented solutions have been successfully applied to the design and resulted in significant improvement in clock distribution quality, design speed, power dissipation and development schedule.

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