Optimizing SoC Design Style and FPGA Implementation Flow for Successful FPGA Prototype Implementation

Abstract
Prototyping of complex SoC designs is a challenging task. SoC design engineers need to provide maximum compatibility between ASIC and FPGA designs, while aiming at maximum prototype clock speed required by real-time critical applications. This paper covers common challenges of targeting to both ASIC and FPGA technologies, and provides solutions and guidelines to address those. It demonstrates what the design engineer should consider in the design to ensure a successful prototype implementation -- the concept of 'design for prototyping'. Also covered is the FPGA design flow, with emphasis on prototyping issues and solutions for designs pushing FPGA technology limits. This includes using the ASIC design engineer's familiar tools to solve the synthesis and verification issues in FPGA domain.

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