An Application of Crosstalk Prevention and Analysis to the Design of a Deep Sub-Micron ASIC

Abstract
The effect of capacitive coupling between neighboring signals in very deep sub-micron (VDSM) ASIC designs is making the analysis of delay effects caused by crosstalk a 'must have' requirement in the ASCIC sign-off process. Without considering crosstalk-induced delay effects in the sign-off process, the design team runs the risk of compromising performance or functionality.

These new sign-off requirements pose a schedule risk if the design team waits for route completion before using an analysis and repair strategy to achieve closure on crosstalk issues. A proactive methodology, which minimizes crosstalk-induced delay effects, has the advantage of reducing the tape-out schedule risk.

In this paper, we share the techniques used in the tape-out of a 0.11um-ASIC design to prevent and analyze crosstalk induced delay issues. By proactively considering crosstalk-induced noise bumps during optimization, we show that post-route signal integrity issues are minimized, resulting in a more predictable design closure.

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