Clock Distribution and Balancing in a Large and Complex ASIC: Issues and Solutions

Abstract
This paper discusses clock distribution and balancing issues in a high-performance and low-power ASIC design. It also presents practical solutions to the issues, based on our experience in a low-power 3G-wireless-application platform ASIC design. The paper focuses on critical topics such as clock-phase delays and skew reduction, maximization of clock-gating effects, operation-mode-dependent clock-delay variation control, clock signal-integrity assurance, and clock-balance-automation-strategy development. The solutions presented have been successfully applied to the design and resulted in a significant improvement in clock-distribution quality, design speed, power dissipation and the development schedule.

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