Top Down Implementation of a 1.6M Gate ASIC

Abstract
This paper describes recent experiences using physical synthesis tools and top-down timing and physical budgeting to complete a 1.6M gate, 0.25u ASIC. The focus of the paper is on the use of floorplanning, top-level routing, physical synthesis, and static-timing analysis tools to minimize, or remove, the need for costly back-end iterations in order to close timing on large designs.

The design in question contains several hard and soft proprietary IP blocks including third-party IP for a PCI controller, on-chip memory BIST and LogicBIST. Top-down timing and physical budgeting is applied to partition the design into 11 functional blocks, including 4 JTAG boundary scan blocks. Block-level placement and top-level inter-block routing occurs early in the process to drive the refinement of the initial timing and area budgets. Each of the blocks is then independently synthesized, placed and routed, using Synopsys and Cadence tools. After all blocks are complete, they are re-assembled and merged with the top-level routing to create a final design that meets the originally-budgeted timing in a single pass.

The methods used are not particularly design specific and can be applied to similar or even larger SoC designs to assist in shortening the overall design cycle.

Since this is a confidential customer design of Synopsys Professional Services, the application in question is not disclosed. The tools and flow used were installed at both the customer's site and at Synopsys' design centers.

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