Timing Closure Methodology for an Imbedded ASIC Design

Abstract
The timing closure of an embedded ASIC design can be challenging due to multiple requirements of chip speed, clock distribution, power consumption and reliable design integration at the chip level.

This paper describes a number of timing-closure techniques successfully applied to a 210MHz & 150k gates generic DMA controller sub-chip designed to be embedded in various ASIC applications. Besides the timing closure flow and placement optimization using Physical Compiler® (PhC), we describe methods that minimize clock phase delays and skews, maximize clock gating effect, improve sub-chip modeling accuracy and eliminate sub-chip -- caused antenna violations at chip-level integration.

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