Efficient Design Flow from System-Level to Hardware in CoCentric® System Studio

Abstract
With the increasing pressure of time to market, it is necessary to have an efficient design flow in place in order to repeatedly achieve successful designs with shorter turn-around times. Also it is important to fully test the behavior of the systems before committing to costly hardware solutions. This paper is based on the flow that is used by Synopsys Professional Services for Wireless Receivers.

The flow has been successfully used from high-level design-done in Cocentric System Studio (CCSS) - followed by RTL implementation and gate-level verification down to successful FPGA prototyping tests for a 3G frequency division duplex (FDD) UMTS wideband CDMA wireless system. The paper highlights the methodology used to rapidly convert algorithmic floating-point system to bit- and cycle-true fixed-point models and finally to actual hardware. It shows that while there is some overhead in terms of the modeling implementation's related functionality; there is a significant gain in terms of re-use of the simulation environment to validate performance at different levels of abstraction. Also there is a gain in speed of RTL-simulation runs when compared to conventional verification methods.

Close This Window