A Hierarchical Implementation Methodology for Large, Complex, Deep Sub-Micron ASICs

Abstract
This paper describes the process by which Corrent Corporation, a startup specializing in the development of high-performance internet security ICs, executed the implementation of a 2.2 Million place-able instance (approx. 6 Million gate equivalent) internet security processor ASIC in a 0.15um process.

To achieve this goal, Corrent had to assemble a talented team, equip them with an effective EDA toolset and unify the team and the tools with a proven implementation methodology. This paper details the methodology that was used to transform the design from RTL to GDSII, paying particular attention to the capabilities of the chosen EDA tools that maximized the quality of implementation results (power, critical path delay, area, testability) and minimized the time required to complete the design.

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