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Abstract In DCPC-Astro design flow the RTL code is first read into Design Compiler to synthesize the initial netlist for floorplanning. The DC synthesis is done with statistical wireload models from design library. DC Synthesis approximates wire lengths, but those seldom correspond close enough with the real wire lengths of placed and routed design. After finishing the floorplan, the design is read to Physical Compiler and the netlist optimization is done based on steiner route wire length approximations, that are very close to the reality. The problem with the DCPC-Astro flow is, that the implementation selections are already done in DC based on statistical wire load models. Therefore it is possible, that the most optimal implementations are not used for the design. This may decrease the performance of the design (max. operating speed) and increase the power consumption and area. To enable PC to make the implementation selections based on more exact steiner routes, we can use a different method through PC-Astro flow. Floorplan can be created based on eg. preliminary DC netlist, and Physical Compiler can start the cell placement and implementation selections from the RTL by using compile_physical command. This results the overall QoR of placed gates netlist to be more ideal than with DCPC-Astro flow with same constraints. |