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Abstract Our AHB bus had 4 AHB bus masters and 4 AHB bus slaves. One of those slaves was an APB bus with 3 APB peripherals on it. Our verification was done in 2 separate phases. One was to write and compile C code for the Power PC processor to execute. We used a Flexmodel for the PPC simulation model. Our second phase used a DesignWare AHB Master VMT model, and an AHB bus monitor. In this environment, we wrote our tests in VERA, and used a combination of constrained random verification, and directed tests to achieve our goals. |