Implementation strategies of a large Xilinx Virtex II Pro Device

Abstract
On a recent project, a team from Synopsys Professional Services designed a large system using a Xilinx Virtex II Pro FPGA. Due to availability of Xilinx parts, we started with XC2VP50, and later moved up to XC2VP70 devices (in the same package). We used the hard Power PC macro, and 4 of the differential Gigabit Rocket I/O Transceivers. We were severely area limited in the 50 device, and had very aggressive timing goals (a large part of the FPGA ran at 125 MHz, with a 64 bit datapath).

For synthesis we used a new Synopsys FPGA synthesis tool (this tool will be announced in March, 2004), and came up with several strategies for improving results and runtime with this tool. We also devised multiple strategies for improving results and runtimes with the Xilinx ISE Software suite. We experimented with Floorplanning, and other physical constraints in the Xilinx ISE tools. Results will be discussed.

This paper will discuss strategies for integrating the PPC CPU and it’s peripherals, as well as Synthesis and Place and Route strategies with the Xilinx ISE tool set.

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