Practical Aspects of Using 3rd Party Semiconductor IP in SoC Design

Abstract
Increased complexity of System-on-Chip (SoC) designs caused by trend towards higher integration and reduced system cost is demanding higher design productivity to manage SoC development cost, time and effort. Semiconductor intellectual property (IP) has become the prevalent form of accelerating the design cycle. However, there are other reasons for IP use such as ensuring interoperability with other components and avoiding design errors with pre-verified blocks. While design reuse is already a common design practice, Gartner Dataquest predicts that by 2005, 80% of SoC consists of reused blocks.

Many design teams have had bad experiences of using 3rd party IP caused by IP quality. With IP, the concept of quality must be considered beyond functional design errors. IP quality also consists of documentation, support, evaluation abilities and ease of integration. In fact, many IP quality issues result of the fact that the IP used has not been originally designed as IP.

With growing SoC development cost and decreasing probability of design success predicted by International Business Strategies, designers’ ability to qualify the used IP in advance is becoming critical and common requirement.

This paper discusses practical methods that SoC designers can use to qualify 3rd party IP. The qualification methods discussed cover:

• Evaluating functional correctness
• Ease of integration with provided implementation tool command scripts and by availability of models especially if source code isn’t available
• Interoperability with standard interfaces
• Ability of IP customization
• Other considerations such as support from IP vendor, documentation, proof of concept and evaluation systems

While specific IP design and verification methods may seem relevant only for IP developers, the growing use of IP requires that SoC design teams can qualify the used 3rd party IP with regards to the quality assurance methods employed.

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