Process-aware Design for Manufacturing (PA-DFM)
Product Family FAQ

General Questions

What is being announced?
Synopsys has announced a new family of process-aware design-for-manufacturing (PA-DFM) products that analyze, at the custom design stage, variability effects for 45-nanometer (nm) and smaller designs. As feature sizes continue to shrink, variability arising from advanced silicon technologies, such as strain engineering, increasingly affects circuit performance. The Synopsys PA-DFM product family’s core products—Seismos and Paramos—address the parametric variations that arise from design and manufacturing interactions, such as layout-dependent stress, proximity effects and silicon process fluctuations.

Why is Synopsys offering these tools?
Process variability presents more and more DFM challenges for designers as new process steps are added for advanced technology nodes. For example, the stress proximity effects arising from strain engineering in 45nm technology nodes and below can significantly impact transistor variations. Unlike litho (OPC/RET) effects currently, strain engineering has no knob to turn for compensation of layout dependency. The PA-DFM products tackle variations arising from advanced silicon technologies, as well as prevailing manufacturing processes at 45nm and beyond. The PA-DFM product family is uniquely equipped to account for transistor variability, a critical capability in the DFM space. The new Seismos and Paramos tools allow custom (IP, cell, memory and analog) designers to optimize layouts and account for variability—in turn, broadening the opportunity to maximize yield. The latest building block in Synopsys’ DFM offering, these new products complement the company’s recently announced PrimeYield suite of yield-analysis tools, as well as its PrimeTime® VX statistical timing analysis and Star-RCXT™ VX statistical extraction tools.

Synopsys recently announced PrimeYield, as well as variation-aware PrimeTime VX and Star-RCXT VX. How does PA-DFM differ from these products?
The PA-DFM tools add to Synopsys’ comprehensive yield-analysis offering. These highly complementary tools, which include HSPICE®, PrimeYield, Star-RCXT VX and PrimeTime VX, uniquely position Synopsys to enable customers to “cover their bases” with respect to variability issues from cell layout through design implementation. These multi-faceted tools address a range of parametric and functional yield challenges by targeting both systematic and random defects at the transistor, gate and interconnect levels.

Can you tell me more about the process-aware DFM products?
The PA-DFM tools address two major sources of variability – proximity variations arising from stress and proximity effects, and global variations arising from the spread of manufacturing process parameters across different die and wafers. The tools enable custom designers to correctly account for manufacturing variability without major changes to their current design flow. The core PA-DFM products are:

• Seismos – simulates and analyzes changes to transistor characteristics due to proximity variations arising from stress and well effects on design layout
• Paramos – extracts process-aware SPICE parameters for detailed analysis of the impact of global variations at the circuit level

How does each of the products work?

• Seismos is a transistor-level tool for the analysis of stress and other proximity effects in nanometer strained silicon technologies. As the 65nm technology node ramps to volume production and the 45nm technology node enters pre-production, customers need the capability to analyze parametric variations caused by proximity effects, such as the impact of layout on transistor stress state. Seismos is the first EDA tool to address this critical need. Its models are based on rigorous TCAD simulations validated by silicon data, and the tool can easily handle multimillion-transistor designs.
• Paramos links SPICE models directly to manufacturing conditions by extracting process-aware SPICE compact models that combine calibrated TCAD simulations and global SPICE extraction. It allows customers to simulate the impact of process variability (statistical or systematic) on circuit performance. This methodology provides customers with a physically based variation model for statistical timing simulations of circuit performance, allowing them to explore a designs’ sensitivity to real physical process parameters.

For process-aware DFM, why is this tool necessary?
To date, DFM efforts have been mostly focused on lithographic effects. However, process variations will increasingly impact circuit performance from 65nm onward due to feature scaling and the use of process steps like strain engineering. Designers need tools that accurately model the different sources of variations and make appropriate changes to the design to guarantee parametric yield. The new PA-DFM tools fill this critical void in the DFM space, allowing custom designers to realize the full potential of technology scaling and to see how much they can push the technology envelope in the design.

What problems do the process-aware DFM products address?
The PA-DFM products deal with the parametric variations caused by design and manufacturing interactions at 65nm and below, such as layout-dependent stress and optical proximity effects, as well as silicon process fluctuations.

Differentiation

What differentiates process-aware DFM products from the competition?
At 45nm and below, customers must understand both the impact and sources of variation. This new PA-DFM product family provides customers with increased understanding of the underlying physical phenomena that cause process variations. In addition, the tools allow customers to take full advantage of Synopsys’ TCAD, DFM and variation-aware statistical analysis technologies to explore and optimize their process and design methodologies, further closing the loop with silicon. Synopsys is the only EDA company that has the expert knowledge in TCAD modeling, advanced process and device engineering, design and EDA to offer this set of PA-DFM products. The PA-DFM product family is uniquely positioned to serve the unmet needs of DFM for 45nm and below.

PA-DFM benefits:

• Links manufacturing variation information back to design, enabling custom designers to optimize layouts
• Allows custom designers to realize the full potential of technology scaling and, in turn, expand the latitude for yield maximization

PA-DFM value:

• Enhances design PREDICTABILITY by
• Minimizing unknown process variations
• Providing variability analysis capability to reduce chip respins
• Increases design PRODUCTIVITY by
• Enabling interactive “what-if” analysis to explore and optimize design layout
• Providing an evolutionary approach to account for variability within existing design infrastructure
• Boosts chip PERFORMANCE by
• Reducing unnecessary guard-bands
• Optimizing design layout to realize the full potential of technology scaling

How do the process-aware DFM products link to other Synopsys tools?
Seismos and Paramos can easily be plugged into the custom “back-annotation” design flow with linkages to other Synopsys tools through GDSII, layout schematic and SPICE netlist. For example, Seismos takes in GDSII and the netlist to start analysis. The input netlist can be either an ideal one generated directly by Hercules LVS, or one with RC parasitics generated by a combination of Hercules and Star-RCXT. In addition, Star-RCXT provides xy coordinates of transistor gates for Seismos to analyze the effects of stress in circuit simulations. For “what-if” analysis, the layout with Seismos stress and other proximity effects can be displayed through IC Workbench. The output of Seismos is a new netlist including device, RC, and stress-related parameters for simulation with HSPICE, HSIM or Nanosim.

In the case of Paramos, the input is the I-V and C-V data coming from TCAD (e.g. Sentaurus Process and Device) simulations. Paramos performs global extractions to generate process-aware SPICE parameters, which in turn will be used for HSPICE, HSIM or Nanosim simulation.

Roadmap

Do the process-aware DFM products replace any existing Synopsys products?
No, the PA-DFM products are new, and they fill a critical void in the DFM space for analyzing transistor variability.

Will the process-aware DFM product family include only Seismos and Paramos, or are there plans to add other products?
Seismos and Paramos are the core products in the PA-DFM product family. However, we plan to add new capabilities and products to address additional process variability issues arising from process scaling at 45nm and beyond.