Simulations of Strained-Silicon CMOS Devices

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Synopsys TCAD has all of the models required to perform process as well as device simulations of modern strained-silicon and silicon-germanium devices.

To demonstrate the capabilities of Synopsys TCAD for strained silicon, both process and device simulations for strained-silicon CMOS devices are presented.

The simulated process is similar to the 90 nm technology with a 50 nm gate length presented by Intel in which a compressive strain is introduced in the PMOS channel using embedded SiGe pockets in the source and drain areas. Tensile strain is introduced in the NMOS channels by using a post-salicide silicon-nitride cap layer.

Sentaurus Process performed the process simulations using implemented strainedsilicon models. These models take into account the strain induced by the lattice mismatch between silicon and Si_xGe_1-x layers as well as the influence of strain and the presence of germanium on the diffusion of the dopants.

The electrical characteristics of the strained-silicon NMOS and PMOS devices were simulated with Sentaurus Device using the strain-induced mobility models to account for the change of mobility in highly strained regions.

Comparison of XX component of stress tensor between NMOS transistor with highly tensile cap layer (left) and device simulated with no-stress cap layer (right); distances are micrometers.

Comparison of I_dV_ds characteristics at V_g = 1.25 V simulated with a strained cap layer and all device strain model (red), with a relaxed cap layer and all device strain model (blue), and without taking any strain effects into account during the device simulation (black).

Comparison of XX component of stress tensor between PMOS transistors with (left) and without (right) Si_0.83Ge0.17 pockets; color bands are the same as above.

Comparison of I_dV_ds characteristics at V_g = -1.25 V simulated with SiGe pockets (red) and without SiGe pockets (blue).