Three-dimensional Simulation of NMOS Transistor

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This project demonstrates three-dimensional simulations of an NMOS transistor including both the process and device parts. The process simulation part is performed using the 3D process simulator Sentaurus Process and the structure editor Sentaurus Structure Editor. A special approach is presented in which all boundarymodifying operations, such as etching and deposition, are performed by a robust geometric engine (Sentaurus Structure Editor), while all implantation and diffusion steps are performed by Sentaurus Process. Robustness and speed are also much improved by the introduction of a "paint-by-numbers" strategy. The drain current versus gate voltage characteristics are computed using Sentaurus Device. Three structures with the same gate length but different widths were simulated. An interesting effect of the trench corner dip shape (divot) on the device performance is observed.

Drain-half of final 3D device structure.

As-implanted 3D Boron profile.

Electrical characteristics for devices with different widths at V_ds=0.05 V. Results are scaled by the nominal device width.

Electrical potential for devices with different widths at V_ds=0.05V and V_gs=0V

Distribution of stress after liner oxidation