Simulation of Laser/Flash Annealing with Sentaurus Process

Full Documentation

This example provides a template for conducting laser annealing simulations in Sentaurus Process. The template simulates a 25 nm gate-length CMOS flow with an added laser annealing step after the conventional rapid thermal annealing (RTA). By comparing the result of this simulation with laser annealing to the one with only RTA, this example demonstrates improved dopant activation by laser annealing, and a correspondingly higher device drive current (approximately 10%) for both NMOS and PMOS devices.

This application note describes the example and highlights several important issues related to laser annealing simulation. The simulation strategy developed for this example can be easily adapted to other custom simulations.

Light absorption/heat generation rate inside the top device region at a certain simulation time. The heat generation rate inside the top silicon region is higher because the silicon absorptivity is larger.

Peak temperature as a function of time; the delay between peak temperature and the lightpulse is approximately 0.3 ms in this example.

Net dopant activation with (solid lines) and without (dashed lines) laser annealing for NMOS (top) and PMOS (bottom). Lines represent net dopant activation at three locations: y = 0.001 µm (red), y = 0.02 µm (blue), and y = 0.2 µm (green).