Three-dimensional Simulations of Strained-Silicon CMOS Devices

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To demonstrate the three-dimensional capabilities of TCAD Sentaurus for strained silicon, both full process and device 3D simulations for typical strained-silicon CMOS devices are presented.

The simulated process is similar to the 90 nm technology with a 50 nm gate length presented in the literature, in which a compressive strain is introduced in the PMOS channel using embedded SiGe pockets in the source and drain areas. Tensile strain is introduced in the NMOS channels by using a post-salicide silicon-nitride capping layer.

A three-dimensional process simulation is performed using "paint-by-numbers" techniques. Sentaurus Structure Editor is used to create the 3D structure and Sentaurus Process performs the process simulations using implemented strainedsilicon models.

The electrical characteristics of the strained-silicon NMOS and PMOS devices are simulated in 3D with Sentaurus Device using the strain-induced mobility models to account for the change of mobility in highly strained regions.

Doping distribution in strained-silicon 3D NMOS transistor.

Comparison of ZZ component of stress tensor (σ_zz) between NMOS transistor with highly tensile capping layer (left) and device simulated with no-stress cap layer (right).

Comparison of I_dV_ds characteristics at Vg = 1.25 V simulated with a strained capping layer (red) and a relaxed capping layer (blue).

Doping distribution in strained-silicon 3D PMOS transistor, SiGe pockets are shown in beige; doping in the pockets is not shown

XX component of stress tensor (σ_xx) after source and drain formation in strained-silicon 3D PMOS transistor

Comparison of I_dV_ds characteristics at Vg = -1.25 V simulated with (red) and without (blue) stress mobility model