TCAD Application Example of the Month
May 2008

Tri-gate Bulk MOSFET Design for CMOS Scaling to the End of the Roadmap

Examples of TCAD Sentaurus in Science and Engineering: IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 5, MAY 2008

Xin Sun (1), Qiang Lu (2), Victor Moroz (2), Hideki Takeuchi (3), Gabriel Gebara (3), Jeffrey Wetzel (3), Shuji Ikeda (3), Changhwan Shin (3), and Tsu-Jae King Liu (1)

(1) Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720-1770 USA (e-mail: sunxin@eecs.berkeley.edu).
(2) Synopsys, Inc., Mountain View, CA 94043 USA.
(3) Advanced Technology Development Facility, Austin, TX 78741 USA.

Abstract

A tri-gate bulk MOSFET design utilizing a low aspect-ratio channel is proposed to provide an evolutionary pathway for CMOS scaling to the end of the roadmap. 3-D device simulations indicate that this design offers the advantages of a multi-gate FET (reduced variability in performance and improved scalability) together with the advantages of a conventional planar MOSFET (low substrate cost and capability for dynamic threshold-voltage control).

The authors relied on TCAD Sentaurus for generation and device simulations of these promising novel three-dimensional device structures. The TCAD Sentaurus simulation project for a sample device is available for download.

View of the simulated 3D tri-gate bulk MOSFET structure with the simulation grid. The nitride spacers are shown semi-transparent to expose the polysilicon gate partially wrapping around the fin-like body

The close-up of the channel area highlights the retrograded well doping profile (dark blue region)

Saturation current density at V_gs=V_ds=1V at a cross-section in the middle of the channel. The effectiveness of top and side walls for current conduction can clearly be seen

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