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NVIDIA Designs Highest Performance 3D Graphics Chip in Less Than One Year With Synopsys Static Verification
"Synopsys' new static verification methodology made a significant contribution to our ability to stay on schedule -- reducing design verification by a factor of three."
Overview The graphics accelerator market is one of the most competitive segments of the semiconductor industry. Getting to market first with the highest performing product is essential to the survival of companies that design and sell them.NVIDIA™ Corporation is no stranger to this market. The Sunnyvale, California-based provider of 3D processors has successfully introduced several generations of graphics processors, including the industry-leading RIVA 128™ in 1997. Surpassing the performance of the RIVA 128 with a new, more powerful chip would be a challenge, but one that NVIDIA had to accept to stay ahead of its competitors. Time to market would be a critical element in the success of the new RIVA TNT™ chip -- the largest non-central processor chip ever produced. Verifying the chip would prove to be the greatest bottleneck in the design flow. To streamline the verification process and hasten time to market, NVIDIA selected Synopsys' static verification methodology, a combination of formal verification and static timing analysis. The biggest challenge was the complexity of the new RIVA TNT chip. With over 7 million transistors and more than 1.5 million gates -- and just one year to deliver a working product -- NVIDIA's engineers faced an almost insurmountable problem. "Even though the TNT design was twice the size of our RIVA 128, we were limited to an equivalent number of engineers in our back-end verification flow. We definitely needed a productivity improvement," said Chris Malachowsky, NVIDIA's vice president of engineering.
Design Decisions If he used a traditional simulation methodology, Malachowsky faced a difficult trade-off of time versus confidence. Spending more time on simulation would increase the reliability of the design, but would jeopardize the schedule and cause NVIDIA to miss their narrow market window. Spending less time on simulation could help the team meet the schedule, but greatly lower their confidence that the design was correct. With just a few months allotted between tape-out and production, re-spins due to undetected design flaws could have a major impact on their production schedule.Malachowsky had successfully used Synopsys' PrimeTime™, a static timing analysis tool, on previous design projects. With the introduction in February 1998 of Formality™, Synopsys' formal verification tool, the Vice President of Engineering saw an opportunity to move to a static verification flow and eliminate the verification bottleneck. When paired in the design flow, PrimeTime and Formality provide a static verification methodology, replacing much of the gate-level simulation required in the past. With PrimeTime statically verifying the circuit timing, and Formality statically verifying circuit function, NVIDIA's designers could exhaustively verify their designs without relying on lengthy gate-level simulations. Using static verification for the RIVA TNT chip reduced design time and increased NVIDIA's confidence. "We've worked with Synopsys over the years, and are confident in the company and its products," said Malachowsky. "We decided that static verification was the best solution for this project." The design team liked PrimeTime's system-level approach, its speed, and its compatibility with Synopsys' Design Compilerlibrary. "PrimeTime provides high capacity and high accuracy. It's the heart and soul of our timing analysis flow," said Malachowsky. Formality made a perfect complement to PrimeTime, delivering a high degree of confidence that allowed the team to make late-stage netlist changes to meet timing goals. Because the two tools were tightly integrated, the design process was easily supported with a very small CAD group.
Meeting Design Goals Because of static verification, NVIDIA was able to meet their aggressive timetable. "Synopsys' new static verification methodology made a significant contribution to our ability to stay on schedule, reducing our verification efforts by a factor of three. The right people with the right tools can do amazing things," said Malachowsky. The RIVA TNT went into production in July 1998. In a very short period of time, the chip began to take market share, and won an important contract when it was selected for use in Dell's desktop computers.The RIVA TNT posts some impressive statistics. In addition to over 7 million transistors, the chip also contains six clock domains and approximately 40,000 flip-flops. The RIVA TNT architecture is the first integrated 128-bit 3D processor that processes two pixels per clock cycle, enabling single-pass, multi-texturing while delivering an astounding 180-million-pixels-per-second fill rate. The TNT chip offers high quality 3D resolutions up to 1600 x 1200 at 30-plus frames per second.
Designing the Future The RIVA TNT will certainly not be the last NVIDIA design using Synopsys' static verification methodology. 3D graphics products will only get more complex, and product cycles will continue to shrink. NVIDIA will continue to use static verification and Synopsys' other tools to bring complex designs to market quickly and cost-effectively. According to Malachowsky, "NVIDIA has chosen very few high-tech partner and we consider Synopsys a key part of our team. Synopsys has repeatedly demonstrated its commitment to our success by providing advanced tools and experience for our toughest design challenges.""Static verification has met NVIDIA's goals for high performance, time to market, and low risk. It's been the right product at the right time for us," said Malachowsky.
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