Overview
Power management has become mission-critical in 130-nanometer designs and below. To speed design convergence, reduce overall fabrication cost, and increase yield, designers today require a comprehensive RTL-to-GDSII solution for dynamic and leakage power optimization, power network synthesis in design planning, power-aware test, power analysis, and power integrity sign-off (voltage-drop and electromigration analysis).
Galaxy™ Power is a complete power management and power integrity sign-off solution for power-efficient design. It is a proven solution for low-power design, optimization, and power integrity. Galaxy Power performs power optimization with support for automatic hierarchical clock gating, multi-voltage designs, multi-threshold leakage, low-power placement and CTS, and state retention power gating, as well as power network synthesis. Vector-free power analysis and sign-off level power integrity, including voltage-drop and electromigration analysis, are also part of Galaxy Power. In addition, Galaxy Power is seamlessly integrated with test (DFT Compiler™ and TetraMAX®), timing (PrimeTime® and PrimeTime SI) and verification (Formality® and VCS®). The full complement of capabilities in Galaxy Power gives designers a predictable and proven solution yielding the lowest power consumption while speeding design closure.
- Key Benefits
- Manages power throughout the entire design flow including synthesis, physical implementation, and sign-off
- Delivers lowest power consumption
- Fully automates the most advanced power management techniques
- Preserves testability, increases yield
- Eliminates power-related failures
- Silicon proven
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