Key Benefits

• Concurrent yield optimization with timing, area, power and SI
• Yield-driven design loss prevention throughout the design implementation flow
• Yield diagnostics enhancement for faster yield ramp
• No impact on timing QOR

The Challenge
With the move to nanometer design, the semiconductor industry has seen an increase in defects and a decrease in target yield … resulting in reduced product margins and missed market windows. Defects arise from such things as lithography errors, process variations, and environmental variations, and can contribute to functional (failing chip) and parametric (out-of-spec chip) yield loss.

The Solution
Since defect mechanisms are evermore dependent on design, not just improvement of the manufacturing process, yield must now be treated throughout the design flow. To address yield loss effectively, a systemic complete solution is required. Synopsys offers the only complete systemic solution available today to address yield loss: Galaxy Design Platform. Galaxy—centered on IC Compiler —provides a comprehensive design-for-yield solution that concurrently optimizes for yield with timing, area, power, signal integrity and routability. Galaxy prevents yield loss optimizes for yield through intelligent design: it understands process and circuit variations and enables defect avoidance to optimize prevent functional and parametric yield loss. Galaxy’s integrated test solution and fault diagnostics flow aid in fast detection of defect mechanisms and effective re-design for faster yield ramp improvement.

For more information about this product, please contact your local Synopsys representative or call 1-800-388-9125.

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