Smart RTL Verification Archive

Press Releases

• Industry Momentum Builds for the ARM-Synopsys VMM for SystemVerilog
• S3 Adopts Synopsys' VCS Verification Solution and the Verification Methodology Manual for Systemverilog
• Synopsys Delivers First Complete SystemVerilog Design and Verification Flow
• Synopsys Announces EDA Industry's First Verification IP Library for SystemVerilog with Methodology Support
• Synopsys' Pioneer-NTB SystemVerilog Testbench Automation Wins IEC DesignVision Award
• Leading Japanese Semiconductor Companies Endorse ARM-Synopsys VMM for SystemVerilog
• AMCC Speeds Verification Using Synopsys' VCS with SystemVerilog and e Testbench Migration
• Exar Triples Verification Productivity Using VCS with SystemVerilog Testbench Automation
• Sun Microsystems and Synopsys Collaborate to Certify VCS Verification Solution for the Solaris 10 OS on x64 Platforms
• Synopsys Introduces Pioneer-NTB for SystemVerilog Testbench
• Synopsys Introduces VCS Verification Library to Speed Verification by up to 5x
• STMicroelectronics Cuts Verification Time In Half with VCS
• VCS Solution Adds Assertion IP Library and Native Testbench
• Huawei Adopts Synopsys VCS Native Testbench
• Top Layer Networks Uses Synopsys' Testbench Automation Solution
• Migration Service from Verisity Specman Elite® to VCS® Verification Solution
• Faraday Verifies Complex CPU Cores with Synopsys' VCS and Vera Verification Solutions
• Crevinn Adopts Synopsys VCS Native Testbench
• Top Layer Uses Synopsys Testbench Automation Tool
• Atmel Adopts VCS Native Testbench
• Aarohi Deploys Synopsys’ VCS Native Testbench
• Synopsys Introduces Migration Service from Verisity Specman Elite® to Synopsys VCS®
• Mentor Graphics and Synopsys Offer SystemVerilog Seminars for Users of the Verisity e Language
• NetSilicon Cuts Verification Time and Effort in Half with Synopsys' Vera Tool
• Synopsys' Magellan Tool Wins IEC DesignVision Award

Articles

• SystemVerilog reference verification methodology: ESL
• SystemVerilog reference verification methodology: RTL
• SystemVerilog reference verification methodology: Introduction
• Transaction-Level Modeling: SystemC and/or SystemVerilog
• Synopsys Announces SystemVerilog Testbench
• The High Cost of Verification
• SystemVerilog verification manual published
• Achieving the Next Productivity Leap
• Coverage is the heart of verification
• Electronic News: Synopsys Woos Verisity Users with Migration Service
• EE Times: SystemVerilog Users Speak Out
• SoC Explorer: Advanced Block-Level Bug-Hunting with Assertion-Based Verification Methodology and Hybrid Formal Verification
• EE Design: Synopsys Claims Enhanced Tool Can Speed Verification by Up to 5X
• Compiler: Verification=IP=Verification=IP=...
• EE Times: Verification, ESL see the same future
• EE Times: Synopsys Tips 'Hybrid' Formal Verification
• EEdesign: Design-for-verification methodology allows silicon success (April 2003)
• EE Times: Synopsys upgrades VCS and Vera (Feb 2003)
• Solving the Design and Verification Challenges of AMBA-based SoCs (Dec 2002)
• Introduction to Assertion-Based Verification (Aug 2002)
• Introduction to SystemVerilog (Oct 2002)