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Synopsys PrimeTime PX

Expanding the PrimeTime Solution with Power Analysis

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Overview
Design closure in today's advanced designs requires a delicate balance of many complex issues. Timing remains critical, but power has become increasingly important as well. Today, with soaring gate counts and increasing design complexities, power management is a mainstream design challenge and a key concern for chip designers. Power consumption is a critical design delimiter. It affects packaging decisions, form-factors, cooling requirements, battery life, design performance, and chip reliability. More than ever, accurate power analysis is critical to avoiding chip failure and achieving design success. The Synopsys PrimeTime® PX solution extends the trusted PrimeTime solution to accurately and quickly analyze power consumption in a design.

The Challenge
Power, timing, and signal integrity (SI) effects are all interdependent at 90 nanometers (nm) and below. To achieve the highest accuracy power analysis, an accurate timing engine is required to perform accurate timing and slew calculations. Prior solutions that included separate, standalone timing, signal integrity, and power analysis tools failed to take advantage of the interdependencies between timing, signal integrity and power. Furthermore, these solutions are not integrated, leading to cumbersome, non-convergent flows that do not achieve design closure.

PrimeTime PX Power Analysis
Synopsys PrimeTime PX, the power analysis extension to the PrimeTime solution, enables full-chip timing, signal integrity and power analysis in a single, easy-to-use environment. Built on the industry's de-facto golden timing standard, PrimeTime PX delivers highly accurate dynamic and leakage power analysis in a shared environment with timing and signal integrity analysis, improving time-to-results (TTR) and productivity over separate, standalone timing and power analysis tools.

By combining timing, signal integrity and power analysis into a single tool and environment, identical operations are not repeated. For example, timing and slew calculations are not repeated. Netlist, parasitic and constraint file reads are not repeated, and tool setup steps are not repeated. As a result, the PrimeTime PX tool delivers up to two times (2x) faster TTR over separate, standalone solutions. Furthermore, as an integral part of the PrimeTime environment, power analysis can be performed using the same PrimeTime commands, reports, attributes and multiple debugging features.

PrimeTime Flow
Figure 1: PrimeTime Suite

PrimeTime Flow
Figure 2: PrimeTime PX Flow—Easy to Use and Adopt

With PrimeTime PX power analysis, the Synopsys Galaxy™ Design Platform offers designers a unified analysis environment for timing, signal integrity and power that is anchored by the PrimeTime tool and provides designers with the highest productivity and a predictable path to silicon for their most complex designs.

Key Features and Benefits

Full-Chip Timing, SI and Power Analysis
The unified analysis environment enables designers to perform accurate leakage and dynamic power analysis along with timing and SI analysis. Power and timing analysis are integrated in a single tool, which improves designer productivity and TTR by providing faster results and fewer set-up steps. With an easy-touse methodology for timing, signal integrity and power analysis, designers can now better understand the trade-offs and effects on these three critical design parameters.

Vector-Free Dynamic Power Analysis
Vector-free dynamic power analysis allows power analysis to be performed without waiting for switching data from simulation. By using the PrimeTime tool's accurate timing windows, vector-free analysis enables precise power analysis early in the design flow to identify blocks with the highest power consumption sooner.

Familiar PrimeTime Flow and Features
As an extension of PrimeTime, PrimeTime PX is easy to use and adopt. It uses the familiar PrimeTime flow, with the same commands, user interface, reports, attributes and capabilities.

Additional Features
  • Event-based dynamic power analysis using VCD or SAIF
  • RTL and gate-level VCD and SAIF support
  • Instantaneous and cycle-accurate peak power analysis
  • Average power analysis
  • State-dependent leakage power analysis
  • Analysis of advanced low power design techniques: multi-voltage, coarse-grain MTCMOS
  • Clock tree power estimation
  • What-if analysis
  • Save and restore
  • Mode/case analysis
  • Voltage and temperature scaling between libraries
  • UPF support
  • Supports industry-standard NLPM and CCS Power libraries
  • Power analysis driver GUI window