SiVL Silicon vs. Layout Verification Tool

Overview
SiVL® is a market leading silicon vs. layout (SVL) verification tool that compares a target design to its simulated silicon image to verify that a design is manufacturable. It is production-proven for obtaining RET closure on subwavelength semiconductor manufacturing processes and chips.

The increasing distortions in the optical and process characteristics which occur in fabrication must be compensated for by increasingly complex OPC and RET modifications of the photomask pattern. This has led to a dramatic increase in the use of OPC and RET techniques (Figure 1).

OPC and RET transforms the photomask pattern into a complex abstraction of the design pattern. The photomask pattern bears little resemblance to the actual silicon result. As a result, checking an accurate simulation of the post OPC / RET photomask pattern against the intended pattern has become crucial to verifying the design and photomask before taking the increasingly expensive and time consuming step of creating masks and printing wafers (Figure 2). SiVL makes sure RET closure occurs ensuring that a designed pattern matches the actual silicon pattern.

Figure 1. Increasing percent of mask layers are using OPC/RET techniques.

Figure 2. SiVL compares a target design to its simulated silicon image to verify that a design is manufacturable.

SiVL Enables RET Closure
SiVL is used first during process development to ensure an optimal lithography and mask synthesis flow. It then verifies that each individual IC design will deliver manufacturable photomasks and optimal lithography results. SiVL’s high accuracy and scalable distributed processing ensure full-chip verification coverage, finding critical errors before production. As a result, SiVL enables development of higher yielding, higher performance processes, more thorough validation of design rules, and reduces expensive silicon respins for production devices—saving hundreds of thousands of dollars in scrapped materials and weeks or months of time to market worth millions of dollars in lost revenue. SiVL is a critical tool for developing and optimizing every subwavelength process and verifying every subwavelength IC taped out on that process.

Key Features SiVL has the key capabilities needed to provide high error coverage to catch real errors while meeting increasingly demanding turn-around-time requirements.

• Uses production proven, high accuracy Proteus simulation and Progen modeling to ensure accurate error identification
• Scalable distributed processing based on Proteus DP technology proven to over 1,000 CPUs
• Check-Figure capability enables checking for actual lithographic problems, not just second order effects such as edge errors
• Shipped with pre-packaged, parameter driven standard checks
• Flexible, easy to use GUI for parameter setup and error filtering
• Powerful underlying language provides full programmability to enable full customization of GUI and checking runset for power users

Unmatched Model Accuracy
The more accurately the simulated silicon represents the actual silicon the lower the probability of missing actual errors or flagging false ones (Figure 3). SiVL leverages the production proven, high-performance, highly accurate, Proteus™ simulation engine and models to simulate the actual post-etch silicon image from the photomask. This enables SiVL to accurately predict and flag real errors such as bridging (Figure 4). The Proteus® models are in use today for production of more than 90% of the world’s subwavelength microprocessors and over 50% of the world’s subwavelength DSP’s and ASICs. They have been proven to have the highest correlation and flexibility of any modeling used in commercially available mask synthesis software.

Figure 3. SiVL’s highly accurate models provide high error coverage.

Figure 4. SiVL accurately predicts and flags real errors, such as bridging.

Figure 5. SiVL’s new “check figure” capability provides extensive checks for likely lithography errors.

Check Figure Capability offers Full-Chip coverage
SiVL’s unique Check-Figure capability ensures full-chip lithography verification coverage within short turnaround times. The Check-Figure feature combines geometricbased and simulation-based checking to look for specific lithographic problems, such as via misalignment and pinching. SiVL identifies areas most likely to have errors, and then applies intensive simulation- based checking using Check-Figures to find and flag actual errors.

SiVL checks for an extensive array of likely lithography errors. Each check can be set up quickly by defining key parameters. Just a sampling of the checks include:

• Pinch or Bridge
• CD Variation
• Line or Slot End
• Contact Overlay
• Mask Rule Checks
• PSM CD Check

Scalable Architecture
SiVL leverages Synopsys’ proven scalable distributed processing in order to ensure optimal feedback within a very short turnaround times. Synopsys distributed processing architecture has been proven scalable on over 1,000 Intel Xeon processors.

Summary
Silicon Versus Layout (SVL) simulation is crucial to enabling RET closure earlier in the process and IC development flow finding lithography errors before expending Hundreds of thousands of dollars and several weeks to fabricate photo masks and chips. SiVL’s proven high accuracy simulation and modeling and robust check figure capability assure key errors are found and false errors are minimized. Proven highly scalable distributed processing meets tight turnaround- time requirements.

Platforms

• Sun Solaris
• HP-UX
• Redhat Linux (IA32, IA64)