HELPING YOU DESIGN THE CHIP INSIDE Products and Solutions ---------- SOLUTIONS ---------- Eclypse Low Power Solution Galaxy Design Platform • Design for Low Power • Design for Test • Design for Yield • RTL Synthesis • Physical Implementation • Sign-Off • Liberty CCS • SDC • Milkyway Discovery Verification Platform • Analysis and Debug Tools • Low-Power Verification • System Analysis & Design • Smart RTL Verification • Functional Equivalence Checking • Mixed-Signal • Languages Intellectual Property (IP) • DesignWare Library • DesignWare Verification IP • DesignWare Cores • DesignWare Star IP • DesignWare Foundry Libraries • IP Reuse Tools Design for Manufacturing • Design-Yield Analysis • Mask Synthesis • Mask Data Preparation • Lithography Verification • TCAD • Manufacturing Yield Management Professional Services • Tool and Methodology Deployment • Pilot Design Environment • Flow Optimization • Implementation • Verification Consulting • Concept to Parts • Core Hardening ---------- PRODUCTS ---------- BSD Compiler: Test synthesis Cadabra: Cell creation Calibration Library CATS: Mask data preparation Circuit Explorer: Analysis & Optimization coreAssembler coreBuilder coreConsultant CosmosLE: Layout design environment CosmosScope: Waveform analysis CosmosSE: Schem. design environment DC Ultra: RTL synthesis Design Analyzer: RTL synthesis Design Compiler: RTL synthesis DesignWare: Design & verif. IP DesignWare Virtual Platforms DFT Compiler MAX DFT Compiler: Test synthesis DSSA Sentry Enterprise: Layout editor ESP: Transistor-level Equivalence Checking Formality: Funct. equiv. checking Hercules: Physical verification HSIM HSPICE: Accurate circuit simulation IC Compiler IC Workbench Innovator: SoC / system modeling JupiterXT: Design planning Leda: RTL checker Library Compiler: Library compilation Liberty NCX: CCS Characterization Magellan: RTL formal verification Memory Solution Milkyway: Design database MVRC MVSIM NanoChar: 90 nanometer & below characterization NanoSim: Fast circuit simulation NanoTime Odyssey Defect/Odyssey YMS Paramos Pilot Design Environment Pioneer-NTB: SystemVerilog testbench automation Power Compiler: Power optimization PrimePower: Power analysis PrimeRail PrimeTime PX PrimeTime: Static timing analysis PrimeTime SI: Signal integrity analysis PrimeYield Tool Suite Proteus OPC PSM-Create & PSM-Check Raphael Raphael NXT Recipe Manager and Editor (RME) Saber: Multi-tech. simulation Scirocco: VHDL simulation Seismos Sentaurus Device Sentaurus Lithography Sentaurus Process Sentaurus Structure Editor Sentaurus TFM Sentaurus Topography Sentaurus Workbench SiVL-LRC: Lithography verification SpiceCheck SpiceExplorer Star-RCXT: Full-chip RC extraction Star-RCXT VX Star-SimXT: Fast circuit simulation System Studio: DSP algorithm design Taurus-Medici Taurus-TSuprem4 TestChip Products TetraMAX: ATPG VCS: Comprehensive RTL Verification VCS MX: Mixed-HDL simulation Vera: Testbench automation WaveView Analyzer DESIGN IMPLEMENTATION VERIFICATION INTELLECTUAL PROPERTY DFM/TCAD DESIGN SERVICES NEWSROOM PLATFORM & RELEASES PUBLICATIONS CUSTOMER EDUCATION SOLVNET SEARCH FOR IP SVP CAFE SNUG CATS™ Optional Products Distributed Processing Lithography Output Options: E-Beam: Cambridge™ Hitachi™ JEOL™ MEBES™ - Now with Mode-5 Support Micronic™ Philips™ Toshiba VSB 8/11 Varian ALF™ Optical Pattern Generator: Electromask English, Metric Mann 3000,3600, Eng., Metric Design Output Options: Applicon™ GDSII Stream™ CIF™ Inspection Options: KLARIS™ Falcon™ Orbot™ Graphical Options: MEBES Job Deck Viewing MEBES Job Deck Editing Hitachi Job Text File Viewing JEOL Job Deck Viewing JEOL Job Deck Editing Versatec™ Plotting Sixel™ (DEC) Plotting Postscript™ Plotting HP-RTL Plotting Metrology Options: SiScan RIF™ Leica LMS-2000 MF2 Leica IPRO Nikon 2I & 3I Control File Zygo KMS KLA-8100 CD-Sem Fracture / Synthesis Options: CATS Jobdeck Smash CATS Keep (polygon selection) MRC: manufacturing rule checks CATS Serif Generation Proximity Correction Options: EBPC: Proxecco™ by aiss, GmbH Sceleton™ by aiss, GmbH CONTACT US  | FEEDBACK  | LOCATIONS  |  PRIVACY POLICY  |  LEGAL

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