HELPING YOU DESIGN THE CHIP INSIDE
Products and Solutions
---------- SOLUTIONS ----------
Eclypse Low Power Solution
Galaxy Design Platform
Design for Low Power
Design for Test
Design for Yield
RTL Synthesis
Physical Implementation
Sign-Off
Liberty CCS
SDC
Milkyway
Discovery Verification Platform
Analysis and Debug Tools
Low-Power Verification
System Analysis & Design
Smart RTL Verification
Functional Equivalence Checking
Mixed-Signal
Languages
Intellectual Property (IP)
DesignWare Library
DesignWare Verification IP
DesignWare Cores
DesignWare Star IP
DesignWare Foundry Libraries
IP Reuse Tools
Design for Manufacturing
Design-Yield Analysis
Mask Synthesis
Mask Data Preparation
Lithography Verification
TCAD
Manufacturing Yield Management
Professional Services
Tool and Methodology Deployment
Pilot Design Environment
Flow Optimization
Implementation
Verification Consulting
Concept to Parts
Core Hardening
---------- PRODUCTS ----------
BSD Compiler: Test synthesis
Cadabra: Cell creation
Calibration Library
CATS: Mask data preparation
Circuit Explorer: Analysis & Optimization
coreAssembler
coreBuilder
coreConsultant
CosmosLE: Layout design environment
CosmosScope: Waveform analysis
CosmosSE: Schem. design environment
DC Ultra: RTL synthesis
Design Analyzer: RTL synthesis
Design Compiler: RTL synthesis
DesignWare: Design & verif. IP
DesignWare Virtual Platforms
DFT Compiler MAX
DFT Compiler: Test synthesis
DSSA Sentry
Enterprise: Layout editor
ESP: Transistor-level Equivalence Checking
Formality: Funct. equiv. checking
Hercules: Physical verification
HSIM
HSPICE: Accurate circuit simulation
IC Compiler
IC Workbench
Innovator: SoC / system modeling
JupiterXT: Design planning
Leda: RTL checker
Library Compiler: Library compilation
Liberty NCX: CCS Characterization
Magellan: RTL formal verification
Memory Solution
Milkyway: Design database
MVRC
MVSIM
NanoChar: 90 nanometer & below characterization
NanoSim: Fast circuit simulation
NanoTime
Odyssey Defect/Odyssey YMS
Paramos
Pilot Design Environment
Pioneer-NTB: SystemVerilog testbench automation
Power Compiler: Power optimization
PrimePower: Power analysis
PrimeRail
PrimeTime PX
PrimeTime: Static timing analysis
PrimeTime SI: Signal integrity analysis
PrimeYield Tool Suite
Proteus OPC
PSM-Create & PSM-Check
Raphael
Raphael NXT
Recipe Manager and Editor (RME)
Saber: Multi-tech. simulation
Scirocco: VHDL simulation
Seismos
Sentaurus Device
Sentaurus Lithography
Sentaurus Process
Sentaurus Structure Editor
Sentaurus TFM
Sentaurus Topography
Sentaurus Workbench
SiVL-LRC: Lithography verification
SpiceCheck
SpiceExplorer
Star-RCXT: Full-chip RC extraction
Star-RCXT VX
Star-SimXT: Fast circuit simulation
System Studio: DSP algorithm design
Taurus-Medici
Taurus-TSuprem4
TestChip Products
TetraMAX: ATPG
VCS: Comprehensive RTL Verification
VCS MX: Mixed-HDL simulation
Vera: Testbench automation
WaveView Analyzer
DESIGN IMPLEMENTATION
VERIFICATION
INTELLECTUAL PROPERTY
DFM/TCAD
DESIGN SERVICES
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Power Window
>
Wire Harness
>
Brake Systems
>
Hydraulic ABS
>
Electrical Power
>
Power Roof
Back to
System Design
Saber for Automotive Systems
Press Releases
>
Synopsys Enhances Saber Simulator Integration with UGS Software Through Global UGS Partner Program
>
Synopsys Qualifies Automotive Industry Standard VHDL-AMS Models for Use With Saber Simulator
>
Volvo Car Corporation Adopts Synopsys' Saber Harness for Automotive Platform Designs
Newsletters
>
The Cutting Edge
Volume 4
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The Cutting Edge
Volume 3
>
The Cutting Edge
Volume 2
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The Cutting Edge
Volume 1
Articles
>
Automotive Design Line: Simulation-based design integration improves hybrid vehicle reliability
>
SAE Off Highway Engineering: Design challenges of off-highway hybrids
> EDN Europe:
Simulation Helps Reduce Design Faults and Warranty Recalls
>
Verification methodology provides robust embedded automotive electronics design
> MathWorks –
Saber-MATLAB Integrations: Enabling HW/SW Co-Verification
>
Modeling Made Easy With New StateAMS Graphical Tool
> SAE ’05 –
Development and Verification of In-Vehicle Networks in a Virtual Environment
>
Driving Vehicle Design Into a New Era
> EDN:
Top 100 products - Saber
>
Test and Measurement World: Create models graphically
>
Fuel Cell Design with Saber
>
Virtual Design of a 42V Brake-by-Wire System
User's Group Presentations
>
Saber Modeling to Support an Electronic Throttle Control Design For Six Sigma Project
(SNUG Detroit 2004)
>
Simulation as an Aid to Worst-Case Design
(SNUG Detroit 2004)
>
Using Parts Gallery to Make Site Specific Components Available to Saber Users
(SNUG Detroit 2004)
>
Using Saber in the CosiMate Cosimulation Environment
(SNUG Detroit 2004)
>
System Simulation with System Studio & Saber Tutorial
(SNUG 2003 Europe)
>
Functional Verification of Mixed Analog-Digital Design Using A Saber/Verilog Co-Simulation Environment
(SNUG San Jose 2003)
>
A Virtual Prototyping for the Netlander Martian Probes EPS - CNES
(SNUG 2002 Munich)
>
An Interactive Design Environment for Delta-Sigma Analog-Digital-Converters
(SNUG 2002 Munich)
>
Behavioural Model of a DCDC Converter Written in VHDL- AMS Hella
(SNUG 2002 Munich)
>
Dynamical Simulation of Electrical Window Regulator Demands on Complete New Verification Approaches Brose Fahrzeugteile GmbH und Co.
(SNUG 2002 Munich)
>
Experiences with SABER Data Sheet Driven Dynamic Power Semiconductor Models
(SNUG 2002 Munich)
>
How Saber Can Help Localize Cerebral Activations
(SNUG 2002 Munich)
>
Reducing Electrical System Design Effort with Automated Design Analysis
(SNUG 2002 Munich)
>
Reluctance Models for Mechatronic System Simulation
(SNUG 2002 Munich)
>
Software Development and Test on Virtual ECU
(SNUG 2002 Munich)
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