|
Overview
Circuit Explorer™ works within leading analog and mixed-signal design environments to bring analog designs and digital cell libraries to
their peak performance and robustness. Circuit Explorer’s Advanced Analysis can quickly simulate designs over all measurements and
corners as well as sweep device sizes allowing the user to gain a deep understanding of the conditions that effect circuit performance.
Circuit Explorer’s Optimization has combined automation with end-user control to allow designers to be fully in command of the optimization,
while removing tedious and time consuming manual modifications to transistor sizing.
- Features
- Analyzes and optimizes, in parallel, over environmental and manufacturing corner conditions
- Sweeps device sizes
- Plots waveforms over sweeps and corners
- Supports batch operation and custom setup through TCL scripting interface
- Generates datasheets
- Optimizes 30+ performance goals simultaneously
- Supports up to 1000 corners during analysis and up to 60 corners during optimization
- Handles up to 200 optimizable device variables (e.g. transistor width, length and multiplier)
- IP Explorer to perform trade-offs, analysis, and see the effects of device sizes on circuit performance
- Benefits
- Substantially improves analog designer and digital library developer productivity
- Rapid retargeting of designs to new or changing performance specifications
- Facilitates process migration and topology and test bench re-use
- Generates numerous optimized circuit results, each with its own performance tradeoffs
- Increases circuit robustness, with circuit performance verified over all environmental and manufacturing process corners
- Manages design and optimization of multiple topologies within a single project
- Facilitates rigorous design methodology
- IP Explorer™ to perform trade-offs and analysis
- Integrated into Design Environments and Simulators
- Imports any custom test bench, measurement,and topology
- Supports hierarchical or flat schematics, all design kits, and all model files
- Automatically imports device size constraints and default ranges from design entry tool
- Allows easy device matching setup, device cross-probing, and back-annotation to design entry tool (Cadence Composer and Synopsys Cosmos SE)
Figure 1. Tightly integrated into existing design flows
- Testbench Setup
- Easy setup and validation of measurements, allowing waveform plotting for test bench validation and inter-test bench connections
- Handles any measurement (e.g., power, noise, area, bandwidth, and stability)
- Optimization Setup
- Selective enabling/disabling of corners on a per-test bench basis
- User specification of device operating constraints
- User specification of performance goals
- Supports Dynamic Steering, allowing setup changes on the fly
- Parallel Computing Architecture
- Supports Platform Computing’s LSF load-sharing environment
- Simulator capacity of up to 100 concurrent simulators (typical users run 5 simulators overnight)
- Multiple automation tasks may be configured and run simultaneously
- Automation Modes
- Supports 3 automation modes:
- Nominal Optimization quickly sizes devices to evaluate topology options and qualifies designs for the next stage of optimization
- Corner Optimization sizes devices to obtain optimal performance across all environmental and manufacturing process corner conditions and readies the circuit solutions for layout
- Full Analysis mode quickly displays the characteristics of any circuit of interest
- Multi-Solution Optimization discovers circuit performance tradeoffs among all performance options
| Circuits |
Optimized Devices |
Device Variables |
Performance Goals |
Design Corners |
| Bi-polar high speed amplifier |
60 |
90 |
15 |
3 |
| USB v2 transmitter |
125 |
132 |
19 |
17 |
| CMOS programmable gain op-amp |
80 |
29 |
21 |
3 |
| Bias generator |
26 |
78 |
12 |
3 |
| CMOS single ended op-amp |
31 |
93 |
26 |
6 |
| USB squelch detector |
60 |
28 |
10 |
3 |
| Gigabit flip flop |
42 |
84 |
15 |
17 |
| Gigabit data receiver |
90 |
45 |
9 |
16 |
| IEEE 1394 data receiver |
17 |
39 |
11 |
32 |
| Gigabit flip flop |
42 |
84 |
15 |
17 |
| Combinational logic cells |
Varies |
Varies |
Varies |
Varies |
| And many more |
|
|
|
|
|
Figure 2. Circuit Explorer Optimization Examples
- Requirements
Computing Environments
- 2 CPU (900 MHz, 512 MB RAM)
- Available for:
- Sun Solaris 8 and 9
- Linux RedHat Enterprise 3.0
Design Environments
- Cadence Analog Design Environment 4.4.5 to 5.10.41
- Synopsys Cosmos 2002.2 to 2004.09
Circuit Simulators
- Cadence Spectre 4.4.5 to 5.10.41
- Synopsys HSPICE 2002.2 to 2006.03
For more information about Synopsys products, support services or training, visit us on the web at www.synopsys.com, contact your local sales representative or call (650)584-5000.
|
