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TSMC is the world’s largest dedicated semiconductor foundry, providing semiconductor companies with advanced process technologies and proven IP to achieve faster time-to-tapeout and time-to-volume.
 BUSINESS OBJECTIVE
TSMC’s proven libraries help speed time-to-volume for semiconductor companies. To expand those libraries with memory IP for advanced nanometer process technologies, TSMC requires verification technology that enables fast turn-around and uncompromising accuracy within the memory design process.
TECHNICAL CHALLENGE
Nanometer effects impact 90 nm memory performance, dictating a critical need for comprehensive full-chip transistor-level post-layout analysis.
RESULTS
With HSIM, TSMC memory designers completed more extensive circuit simulations needed to ensure silicon success of IP for advanced 90 nm SRAM, 1T-RAM and Flash memory. Semiconductor companies look to Taiwan Semiconductor Manufacturing Company (TSMC) for the industry‘s most advanced process technologies and a ready portfolio of proven intellectual property (IP). When TSMC faced growing challenges in verifying next-generation memory IP blocks, the semiconductor leader turned to HSIM for proven nanometer verification technology able to handle massive amounts of data, reduce turn-around time and deliver results with uncompromising accuracy. Using Synopsys’ HSIM hierarchical circuit simulator, TSMC memory IP experts found they could easily complete more transistor-level, post-layout verification runs needed to ensure performance of next-generation nanometer memory designs.
Challenge
With nanometer technologies of 90 nm and below, exhaustive transistor-level post-layout verification is essential for accurately predicting performance of advanced designs. At these geometries, nanometer effects such as parasitic coupling significantly degrade dynamic performance. Yet, this detailed analysis brings a flood of extracted parasitic data that at best severely slows down performance of traditional circuit simulation tools—and at worst simply overwhelms the capacity limitations of those tools. Next-generation 90 nm memory designs compound these critical verification challenges with faster clock rates, high-density cells and individual blocks comprising up to tens of millions of transistors. To expand its extensive libraries of proven memory IP for its latest process technologies, TSMC needed verification technology able to deal easily with massive amounts of post-layout data and quickly turn around SPICE-accurate results on multi-million transistor designs.
Application
As an industry leader in semiconductor manufacturing, TSMC helps semiconductor companies achieve rapid time-to-tapeout and time-to-volume with its broad array of proven, process-specific libraries. Each advance in process technology brings a related development effort for TSMC memory IP designs to prove out the process and meet continual customer demand for higher density embedded memory. For TSMC’s advanced 90 nm process technology, TSMC designers looked to create new SRAM, 1TRAM and Flash memory IP in blocks as large as 32 Mb. To verify the new IP and associated test chips, TSMC needed correspondingly more advanced verification methods to deliver accurate performance results for these nanometer designs.
"Conventional verification tools are either too slow in terms of turn-around time or are not able to handle the large amount of data associated with advanced memory designs," said Mark Chen, Design Service Director. "For us, simulation accuracy and fast turn-around time are critical."
In the past, engineers could partition large designs using SPICE cut netlists and analyze designs section by section. Besides introducing human error, this approach inherently suffers from accuracy problems and its inability to analyze power. For nanometer designs in particular, this limited approach to verification lacks the comprehensive analysis needed to determine performance in the face of coupling effects in nanometer designs. To address its growing nanometer verification challenges, TSMC enhanced its existing design flow with more sophisticated verification technology from Synopsys.
Methodology
For advanced nanometer designs, an effective verification methodology requires the ability to quickly deliver SPICE-accurate results on complete designs. As memory designs increase in size, conventional SPICE simulators are unable to handle the large post-layout simulations needed to account for nanometer effects and accurately verify performance. Designers can no longer rely on limited analysis of separate circuit sections using SPICE-cut netlist methods. Accuracy depends on full-chip transistor-level simulation of post-layout designs–an increasing challenge as design files continue to swell in size with postlayout RC elements.
"Advanced technologies require special design attention to the interconnect RC elements," said Chen. "But post-layout circuit simulation includes large volumes of R, C and MOSFET device elements, which causes problems for some tools."
With its hierarchical simulation technology, HSIM easily handles the largest designs with full post-layout data. And because HSIM directly uses SPICE netlists, it fits smoothly into existing design flows, replacing older SPICE-type tools in existing design and verification flows. Just as important, HSIM delivers SPICE-accurate results on complete designs in a fraction of the time needed even for much smaller circuits that could be simulated with earlier SPICE-type tools. In the face of shrinking market windows and growing competitive pressure, HSIM’s capacity for full-chip designs means more exhaustive verification, and its faster turn-around time means more simulation runs—all needed to achieve greater confidence in tapeout and early silicon success.
"Design complexity and demand for more accuracy are constantly our challenges, and HSIM's fast simulation time and large database handling capability help us overcome these challenges with great efficiency," said Chen. "HSIM gives us the capability for whole chip simulation, while other tools for the same purpose are not as competitive in terms of speed and data handling."
Results
HSIM helped TSMC designers work more effectively, completing more extensive verification on their 90 nm memory designs to accurately determine key performance characteristics including access time, standby current and active current characteristics for the designs.
With HSIM, TSMC engineers completed critical path simulations in just four hours for an 8 Mb SRAM design. And in just 24 hours, HSIM completed full-chip post-layout verification of a 512K SRAM design with a 1 GB netlist file. HSIM’s advanced verification capabilities enabled TSMC designers to perform more comprehensive verification in less time, leading to early silicon success.
"With HSIM full-chip simulation, we achieved functional silicon in a 90 nm 8Mb SRAM test chip," said Chen. "HSIM’s fast design turn-around time and ability to handle large databases make it an effective replacement for earlier SPICE tools, and going forward we will use HSIM to design 90 nm 1T-RAM embedded DRAM with memory capacity greater than 64Mb."
Summary
Targeting TSMC’s advanced 90 nm process technology, new IP for SRAM, 1T-RAM and Flash memory exceeded the capabilities of traditional verification tools. To account for the increased influence of interconnect on circuit performance, TSMC designers needed the ability to complete full-chip transistor-level post-layout simulations of their nanometer designs. HSIM’s advanced verification technology allowed TSMC designers to complete critical simulations in a fraction of the time required by earlier tools–and rapidly achieve working silicon in chips intended to prove out the advanced 90 nm technology and new memory IP designs.
About TSMC
Taiwan Semiconductor Manufacturing Company (TSMC) is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry industry’s largest portfolio of process-proven library, IP, design tools and reference flows. The company operates one advanced 300mm wafer fab, five eight-inch fabs and one six-inch wafer fab. TSMC also has substantial capacity commitments at its wholly-owned subsidiary, WaferTech, and its joint venture fab, SSMC. In early 2001, TSMC became the first IC manufacturer to announce a 90-nm technology alignment program with its customers. TSMC’s corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC, please see http://www.tsmc.com.
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