CosmosLE Intelligently Automated Full-Custom Layout Environment

Overview
Significant designs, notably system-on-chip (SoC), contain custom, mixed-signal, and analog components that require schematic capture, simulation, and physical-layout design automation in addition to standard-cell blocks that are based on synthesis and automated place and route. Most designs interface to the analog world, and market pressures often require highperformance capabilities that can be achieved only with a full-custom, handcrafted-layout design environment such as CosmosLE™.

CosmosLE™ uses core capabilities of Enterprise™ and schematic-driven layout (SDL) to place and route full-custom circuits and is a perfect complement to CosmosSE’s schematic-based simulation and analysis. The designer controls the level of layout automation, ranging from automated layout to full-featured, handcrafted layout. Intelligent layout automation in CosmosLE results in LVS- and DRCcorrect cell and macro layouts.

CosmosLE Benefits

• Prevents ECO Errors and Time-Wasting Data Translations. CosmosLE provides the only SoC solution residing on a common database. By using Synopsys’ common database, Milkyway,™ design time is not wasted on intertool data translations requiring GDSII stream in or stream out. Engineering change orders (ECOs) are handled easily without meticulous updates to multiple databases.

• Reduces Design Time. CosmosLE schematic-driven layout automates the instantiation and placement of components. Automatic instantiation of devices with built-in connectivity dramatically reduces layout time.

• Provides DRC- and LVS-Correct Place and Route. Adherence to incredibly complex geometrical rule sets is no longer a problem for the layout designer. New technologies in CosmosLE provide built-in design-rule awareness to prevent design-rule violations during place and route.

• Allows In-Process Sign-Off Physical Verification. CosmosLE allows layout designers to conveniently run Hercules™ and Hercules LVS and DRC sign-off physical verification from within their layout environment. Additionally, Cosmos™ allows use of Hercules Explorer to repair DRC, LVS, or ERC errors.

• Maintains Signal Integrity. Tedious tasks such as shielding and guardbanding are automated, thereby allowing designers to rapidly create layouts, extract parasitics, and verify signal integrity via simulation with CosmosSE and HSPICE® or NanoSim™.

CosmosLE provides automation and integration directly within the Enterprise custom layout editor with tight coupling to the CosmosSE mixedsignal design analysis environment.

Cosmos is the only full-custom solution on the Milkyway database, allowing sharing and consistency of process data with Astro, Venus and Columbia.

Today’s mixed-signal design processes become increasingly complicated as minimum fabrication dimensions reach sizes that are a fraction of the wavelength of visible light.

Correspondingly, the design rules required for high fabrication yields have become too complex to manage with older, lessautomated electronic-design-automation (EDA) tools.

From a designer’s perspective, the size and complexity of SoC designs are increasing exponentially. Meeting the dual challenges of fabrication effects and design constraints requires EDA tools that increase designer productivity while handling these complex issues. CosmosLE offers significant advantages, such as the Milkyway common database, automated schematic-driven and netlist driven layout, and automatic place and route capability, to increase layout productivity and efficiency.

Precision circuits designed with CosmosSE and HSPICE require careful placement and routing to preserve the speed and performance realized in the simulation environment. Special techniques used by analog and mixed-signal designers, such as shielding and guard-banding, are supported to avoid crosstalk errors and stray-charge injection.

CosmosLE, with intelligent automation, provides the flexibility required for analog design, but reduces the effort required for LVS-correct and DRC-correct layout design.

Milkyway Advantage
Synopsys’ CosmosLE is the only fullcustom design solution residing on a common database. Because Cosmos maintains both schematics and layout in the Milkyway database, changes such as ECOs are made once. No data translation between point tools occurs. Costly engineering time is conserved. In addition to the advantages of a common database, common technology files allow sharing and consistency of process data with other Milkyway-based tools such as Hercules and Astro™.

Typical of CosmosLE’s highly productivity features, routes can be dragged between multiple views of the same cell.

Schematic-Driven Layout (SDL)
Full-custom designers work with circuit schematics to specify, simulate, and analyze their designs. Circuit schematics are the de facto standard for custom, mixed-signal, and analog design specification. CosmosLE uses SDL to instantiate schematic devices into layout using programmable cells (pcells) written in Tcl. The instantiated and placed devices inherit net names and connectivity from the schematic. SDL provides an automated and flexible capability for the custom physical designer to rapidly create layouts that meet performance specifications.

Advanced Automated Place & Route
Advanced technology handles the instantiation and placement of schematic devices in layout considering schematic properties and programmable cell parameters. It provides on-the-fly flexibility for device sizing, aspect ratio, rotation, reflection, and strapping of gates, sources and drains. The automatic router moves, aligns, and arrays devices with flexibility, speed, and design-rule correctness.

Automation technology uses schematicspecified connectivity to create design-rule correct interconnections. Interconnects are excluded from design-rule-incorrect areas. A mouse click is sufficient to create vias and stacked vias. When necessary, TopoRoute pushes blocking routes aside to complete a path. In-route display of estimated parasitic capacitance and resistance is supported.

Advanced automated place and route technologies are standard within CosmosLE, not extra-cost options.

Physical Verification and Extraction
Support for Synopsys’ Hercules sign-off LVS, DRC, and ERC physical verification is integrated within CosmosLE. Also, Hercules Explorer allows in-place analysis, diagnosis, and repair of violations directly within the layout environment.

With the Milkyway common database and Star-RCXT™ extraction, layout parasitics can be back-annotated onto a schematic. In the complementary CosmosSE environment, such back-annotated netlists are accurately simulated using HSPICE and NanoSim.

Cosmos Offers Complete Front-to-Back Solution
CosmosLE works seamlessly within the Milkyway-based, Cosmos environment to provide integrated front-to-back, custom, mixed-signal, and analog circuit design capability. CosmosSE supports schematic capture, simulation, and analysis. CosmosLE with SDL provides an automated path from the schematic-capture system to custom layout. Also within CosmosLE, a full-featured custom editor is available to create or modify design layouts. Finally, advanced simulation-based analysis with back-annotated parasitics and full-cross probing to layout is supported within the Cosmos environment.

Because both schematics and layout are integrated into the Milkyway common database within Cosmos, schematic and layout are always in sync. Notification is provided should a change to either schematic or layout cause loss of synchronization.

For legacy designs, Synopsys provides an easy migration path to Cosmos and Milkyway via EDIF translation.

IC Power Users Choose Synopsys Technology to Create Advanced Technology Designs
Synopsys’ advanced custom-design-automation technology is the choice of IC power users for creation of ultra-deep-submicron (UDSM) designs. In the standard-cell market Synopsys leads the way with Astro. Adding Cosmos full-custom design capability to Astro standard-cell design capability provides complete SoC design automation.

Synopsys’ JupiterXT™ hierarchical design planning provides partitioning, block placement, and timing budgeting. In the partitioning and placement step, JupiterXT provides area and pin information that can be used to constrain Cosmos physical layouts. When Astro standard-cell blocks and Cosmos full-custom blocks are complete they are assembled onto a full SoC using Synopsys’ Columbia™ top-level chipassembly capability. Hercules’ sign-off LVS and DRC physical verification are supported both within Cosmos and from Milkyway for final tape-out verification. Cosmos is an advanced, full-custom solution available as an integral part of the Milkway-based, SinglePass-SoC™ solution. <> CosmosLE is available on 64-bit platforms to directly support the largest SoC designs without partitioning, a significant advantage.

CosmosLE (2001.4 Release) Supports the Following Platforms:

• Unix SUN 32 and 64 bit
• Unix HP 32 and 64 bit
• Linux 32 bit

For more information about Synopsys products, support services or training, visit us on the web at www.synopsys.com, contact your local sales representative or call 650.584.5000.