SpiceCheck is a transistor-level static netlist checker that helps designers meet the verification challenges of today’s complex ICs, which involve low-power, multi-rail high-speed designs. Problems that are difficult to detect by Spice transient simulations -- like missing inter-domain level shifter, constant-on leakage path and max nodal-voltage checks, for example -- can efficiently be addressed by SpiceCheck. Full Tcl programmability coupled with built-in verification rules makes SpiceCheck flexible for different design types yet delivers out-of-the-box productivity.
- Benefits
- Visualize electrical impact of interconnect
- Features
- Programmable Tcl check commands for full customization
- Netlist traversal and device parameter access
- Multi-domain checks for missing level shifter
- Static DC bias estimation
- DSPF correlation to ideal net
- DSPF net resistance calucation
- Netlist topology finder
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