Design Compiler Graphical Extending Design Compiler topographical technology to predict and alleviate routing congestion

Overview
Design Compiler® Graphical extends DC Ultra™ topographical technology to predict circuit congestion “hot spots” early in the design flow, provide designers with visualization of congested circuit regions and perform specialized synthesis optimizations to minimize congestion in these areas. It is the industry’s only synthesis solution that enables RTL designers to avoid wire-routing congestion problems that occur during detailed route. This ability to predict, visualize and alleviate routing problems prior to physical implementation substantially reduces iterations between synthesis and place-and-route, and can significantly lower project time, effort and cost.

Design Compiler Graphical shares technology with Synopsys’ IC Compiler and provides RTL designers an early view into a design’s wire-routing congestion characteristics. It allows designers to identify potential congestion issues and fix them earlier while still in the synthesis phase. It includes a new layout view that provides an interactive mechanism to debug timing issues related to the designs layout as well as detect and debug sources of congestion. Once identified, RTL designers can then make the necessary changes to alleviate wire-routing congestion in their design either automatically by enabling congestion optimization capability in Design Compiler Graphical, changing the floorplan or by changing the RTL. The result is a netlist that is a better starting point for physical implementation leading to faster place-and-route. By extending topographical technology in DC Ultra, Design Compiler Graphical empowers RTL designers to predict post-layout timing, area, power and testability, as well as congestion during RTL synthesis.

Key benefits

• Improved schedule predictability with accurate congestion prediction in synthesis
• Faster design convergence with early detection and debugging of layout issues using physical visualization
• Reduced routing congestion with new specialized congestion driven optimizations
• Faster physical implementation with easy-to-route netlist
• Concurrent Multi-Mode synthesis

Growing design complexity can lead to higher design congestion
With increasing demands on design functionality coupled with shrinking device sizes, wire-routing congestion issues can result in designs that are difficult to route and can lead to substantial schedule delays. Design congestion occurs when the resources (tracks) needed to route the design exceed available resources. In other words, certain areas of designs are congested when the number of physical wires needed to connect the gates that make up the logic exceeds the space available between the gates to route the wires.

Figure 1: Congestion map

Without Design Compiler Graphical, a design’s wire-routing congestion ‘footprint’ is not available until well into place-androute. This footprint is called a congestion map and the color distribution of the map indicates the relative routability of the design. Large concentrations of white and red indicate areas of high congestion, with blue representing the least-congested areas. Figure 1 shows a congestion map generated after layout. As indicated by the amount of red in the congestion map, a significant portion of the design is congested. There is a very high likelihood that this design will have trouble routing.

During place-and-route, designers deploy various techniques to alleviate congestion. These techniques can include changes to the floorplan, such as port or macro locations, changing target gate utilization, etc. Making such changes during placeand- route is time-consuming and can lead to schedule delays. Changing the floorplan late in the design cycle during placeand- route can lead to other problems, such as timing convergence. Further, these techniques may not work and the designer may be required to go back and recode the RTL source of the congestion to achieve the required results.

Figure 2: Design Compiler Graphical results

These options are not optimal and can lead to missed schedules, missed design goals and result in added costs.

Extending topographical technology to accurately predict congestion
Design Compiler Graphical includes Synopsys’ virtual globalrouting technology that enables designers to predict wirerouting congestion during RTL synthesis. This technology allows designers to identify and fix design issues to reduce place-and-route congestion, potentially eliminating costly iterations between synthesis and physical implementation to achieve the design goals and speed up place-and-route.

Figure 2A shows a congestion map predicted by Design Compiler Graphical and Figure 2B shows the congestion map in IC Compiler after optimizing the design in place-and-route to reduce congestion. It is clear that Design Compiler Graphical is able to identify the design’s highly-congested areas during RTL synthesis, thus providing designers with valuable information on the design’s ability to route during place-and-route.

Figure 3: Interactive analysis of congestion map in Design Compiler Graphical

Early physical visualization
Design Compiler Graphical also includes a new physical viewer that allows RTL designers to view layout congestion in their design during synthesis, as shown in Figure 3. Design congestion that is related to the floorplan, such as macro placement or port location, cannot be automatically optimized in synthesis. These congestion issues can only be resolved by changing the floorplan. Using Design Compiler Graphical’s physical viewer, designers can identify floorplan issues such as sub-optimal macro or port locations, as well as congestion “hot-spots”, and take corrective measures to alleviate congestion problems before place-and route.

Figure 4: Design Compiler Graphical physical view

These interactive visualization capabilities also include the ability to cross-highlight suspect physical cells in the congestion map to the netlist, as shown in Figure 4. This allows the designer to easily isolate problem timing paths and make necessary changes during RTL synthesis.

Figure 5: Design Compiler Graphical and IC Compiler congestion maps

Congestion-driven optimization in synthesis
Once it is identified that the design is congested and the congestion is not related to the floorplan, the next step is to fix the congestion in synthesis. Design Compiler Graphical provides an automated way to optimize the RTL to reduce placeand- route congestion. It performs specialized optimizations to generate a routing-friendly netlist topology that minimizes highly-congested structures and wire crossings in congested areas. By intelligently choosing netlist structures that are easier to route, Design Compiler Graphical can generate a netlist that is a better starting point for physical implementation, leading to faster place-and-route.

Figure 5A shows the congestion characteristics of the same design highlighted in Figure 2A. Figure 5B shows this design after optimizing the design to reduce congestion using Design Compiler Graphical. It clearly shows that the congestion optimization technology has significantly reduced wire-routing congestion in synthesis, resulting in a design with minimal to no layout congestion as shown in Figure 5C after placement in IC Compiler. Design Compiler Graphical has automatically optimized this design to minimize wire-routing congestion by taking into consideration the congestion characteristics of the synthesized cells.

Multi-Mode synthesis
Today’s complex designs also contain multiple modes, such as scan mode, BSCAN mode, mbist mode, sleep mode, several functional modes, etc. Optimizing serially across each mode can be time-consuming and require multiple iterations to achieve optimal results. With Design Compiler Graphical, RTL designers can analyze and optimize designs across multiple modes concurrently to substantially drive down design development time and cost.

Easy to adopt
Design Compiler Graphical is designed for seamless integration into the current RTL synthesis use model. It uses the same setup as DC Ultra topographical technology. Similarly, it is designed for RTL designers, does not require deep physical design expertise, and improves productivity by enabling more informed decisions during RTL synthesis with early visibility into what the design characteristics will be during place-and-route. The inputs to Design Compiler Graphical, which are the same as DC Ultra with topographical technology, are listed below and also shown in Figure 6:

• Design RTL
• Logical Library (db)
• Physical Library (Milkyway™)
• Design constraints (SDC)
• Optional physical constraints (Floorplan)

Figure 6: Design Compiler Graphical inputs and outputs

The output is a netlist optimized for timing, area, test, power and congestion with accurately-predicted layout results, ready for physical implementation hand-off.

Conclusion
Design Compiler Graphical significantly boosts RTL designers’ productivity. It provides the ability to accurately predict, visualize and alleviating routing congestion, creating a better starting point for place-and-route. In doing so, it substantially reduces iterations between synthesis and physical implementation, resulting in a predictable implementation flow with faster placeand- route.

Availability
Design Compiler Graphical is available now as an add-on to DC Ultra.