Design Compiler Ultra Design Compiler at its Best

Overview
Design Compiler Ultra (DC Ultra) is the best-in-class, production RTL synthesis solution enabling users to meet today's design challenges such as fastest timing, smallest area, lowest power consumption and highest test coverage in the shortest design cycle time. DC Ultra achieves this by concurrently applying its unique algorithms to optimize for timing, area, power and test.

Innovation in synthesis has always been synonymous with Design Compiler. Continuing the trend, Synopsys now offers the latest innovation in synthesis: Design Compiler topographical technology. Topographical technology enables a predictable flow resulting in faster time to results by eliminating costly iterations between synthesis and layout. It accurately predicts post-layout results such as timing, power and area in synthesis while eliminating the need for wireload model-based approximations.

Key benefits are:

• Delivers best Quality of Results (QoR) in terms of area, timing, power and test
• Correlated to physical implementation
• Removes timing bottlenecks by creating fast critical paths
• Offers more flexibility for users to control optimization on specific areas of designs
• Distributed synthesis with automated chip synthesis
• Enables higher efficiency with integrated static timing analysis, test synthesis and power synthesis
• Support for multi voltage and multi supply

Figure 1: The industries most comprehensive synthesis solution.

DC Ultra is the core of Synopsys' comprehensive RTL synthesis solution, including Power Compiler™, DesignWare®, PrimeTime®, and DFT Compiler. It is built upon the industry leading DC Expert synthesis engine, offering all the benefits of DC Expert in addition to its own unique advantages.

Figure 2: The Latest Innovation in RTL Synthesis

Topographical Technology—the Latest Innovation in Synthesis
Topographical technology, the latest innovation in synthesis, delivers accurate correlation to post-layout timing, area and power without the need for wireload models. It is designed for RTL designers and requires no physical design expertise or changes to the synthesis use model (Figure 2). The accurate prediction of layout timing and area in DC Ultra is achieved through the innovative “topographical technology”. It enables RTL designers to fix real design issues while still in synthesis and generate a better start point for physical design, eliminating costly iterations. This significantly boosts RTL designers' productivity. Topographical technology shares technology with Galaxy™ physical design, ensuring a smooth, convergent path from RTL to GDSII.

Advanced Arithmetic Optimization
For designs containing datapath, DC Ultra provides better QoR in terms of timing and area in less synthesis runtimes for datapath through innovative datapath optimization algorithms. With these capabilities, DC Ultra identifies arithmetic trees in your HDL and optimizes them using carry-save arithmetic techniques to minimize performance and area impact of carry propagation (Figure 3).

With DC Ultra, logic synthesis users can also take advantage of superior datapath synthesis capability to generate highly optimized implementations of DesignWare arithmetic components.

Figure 3: Transformation of sum of products into a Carry Save Adder (CSA) tree

Powerful Critical Path Synthesis
DC Ultra employs various optimization algorithms throughout the synthesis process to deliver ultra-fast critical path timing. For example, immediately after the initial technology mapping, the design is not yet subjected to detailed gate-level optimization techniques. At this stage, DC Ultra performs aggressive timing driven restructuring, mapping and gate-level optimization. As a result, the subsequent detailed gate-level optimizations benefit from better overall timing-based structure. Throughout gate-level optimization, additional strategies are applied to improve the delay of the critical paths in the design. One of the techniques includes aggressive logic duplication for reducing the load seen by the critical path (Figure 4). DC Ultra looks at a larger subsection of the critical path during logic duplication and can replicate many gates to reduce load of high fan-out nets, hence improving timing on critical paths through load isolation. DC Ultra will also automatically ungroup parts of the design on the critical path to achieve better area and timing. It can also buffer high fanout nets to improve total negative slack.

Figure 4: Through logic duplication, DC Ultra reducesthe load on
the critical path for significant timing improvements

The DC Ultra mapping algorithms also attempt to map groups of cells to wide-fan-in library cells on critical timing paths that can reduce number of logic levels and cell instances. Thus, timing, area, and power are improved.

Register Retiming
Register retiming further improves QoR. It performs optimization of sequential logic by moving registers through logic boundaries to optimize timing with minimum area impact (Figure 5) for designs that already contain registers. The same functionality is preserved at I/O boundaries. Register retiming can also insert pipeline registers in pure combination circuits to be used to meet performance requirements as well as reduce area (Figure 6). Register retiming can be used along with datapath optimization algorithms to get the fastest pipelines.

Figure 5: Retiming designs with registers

Figure 6: Retiming on combinational logic

Better Control of Synthesis Cost-Function Priorities and Optimization Steps
DDC Ultra provides finer control over optimization to meet aggressive timing requirements. DC Ultra has a default cost function that prioritizes design rule requirements over timing and area constraints. By setting the appropriate priority, designers can drive synthesis to achieve the best QoR for a design. Compile directives in DC Ultra can be used to further control optimization. The compile directives allow the designer to change DC Ultra's standard behavior. For example, a designer may have a particular structure in mind and have instantiated the cells in the path. Although the overall structure should not change, it may be desirable for Design Compiler to perform sizing and local optimization for better timing. For this set of optimizations, the global structuring of the logic can be disabled while enabling gate sizing.

Netlist Formats and Interfaces
DC Ultra supports all popular industry standards formats.

Circuit Netlist:
Verilog, SystemVerilog, and VHDL
Command Script: dcsh, TCL

Interfaces:
PLI, SDF, PDEF, SDC

Platforms:
HP-UX (32-/64-bit)
IBM AIX (32-/64-bit)
Redhat Linux (32-/64-bit)
Sun Solaris (32-/64-bit)

Summary
DC Ultra is the synthesis solution for today's designs offering best-in-class QoR. With its unique and comprehensive optimization algorithms, correlated QoR to physical implementation with topographical technology, added user controllability, and a proven track record of countless design successes, DC Ultra continues to be the best synthesis solution for all design needs.