IC Compiler The next-generation physical design system

Overview
IC Compiler is an integral part of the complete Galaxy™ Design Platform that delivers a complete design solution from synthesis to design for manufacturability. It is a single, convergent, chip-level design tool that enables designers to implement high-performance, complex and challenging designs. As a widely adopted solution, IC Compiler provides best-in-class Quality of Results (QoR), tight sign-off correlation and powerful Design for Yield (DFY) capabilities.

• IC Compiler uses Extended Physical Synthesis (XPS), a significant new capability that extends physical synthesis to full place-and-route. XPS enables faster turnaround time (TAT) as well as better QoR, measured in terms of the complete cost vector-timing, area, power, signal integrity, routability, and yield.
• IC Compiler is tightly correlated to the industry-standard sign-off solutions-PrimeTime-SI® and Star-RCXT™. Additionally, it utilizes these signoff engines to achieve fast, accurate signoff-driven design closure during the final changes of physical design implementation. Signoff-driven design closure further increases design predictability.
• IC Compiler provides a comprehensive DFY solution that concurrently optimizes for yield with timing, area, power, test, and routability. IC Compiler increases manufacturability of the design, optimizes for yield and enables defect avoidance to reduce functional and parametric yield loss.
• IC Compiler has powerful design planning and chip-level analysis features to handle large, complex designs. It provides early analysis and feasibility exploration capabilities to achieve smaller die size and reduce cost of design.

Benefits
QoR
XPS enables new and innovative technologies in IC Compiler that unify synthesis, placement, clock tree synthesis, and routing to deliver increased QoR, measured in terms of the complete cost vector-timing, area, power, signal integrity, routability, and yield. New technologies like concurrent multi-corner multi-mode (MCMM) optimization, enhanced signal integrity capabilities and physical datapath help meet aggressive QoR targets for large, complex chips.

Turnaround Time
IC Compiler provides the fastest path to results. This is achieved by using powerful design planning capabilities, complete convergence throughout the design stages, and a seamless RTL-to-GDSII flow.

Figure 1. Physical datapath increases predictability and reduces power.

Figure 2. Thermal map based on PNS and IR drop

• Design Planning: IC Compiler has powerful design planning and chip-level analysis capabilities to handle large, complex designs. It is intended to be used for both a fast exploration of the design to reduce die size and to implement a final, optimized, and detailed floor plan.
• Correlation: IC Compiler is tightly correlated to the industry standard sign-off tools, PrimeTime-SI and Star-RCXT. IC Compiler shares delay calculation modules with PrimeTime/PrimeTime-SI such as cell delay, Arnoldi wire delay, Composite Current Source (CCS) models, and features like Clock Reconvergence Pessimism Removal (CRPR) and On-Chip Variation (OCV) to achieve the tightest correlation to signoff in the industry. In the final stages of design closure IC Compiler utilizes PrimeTime-SI and Star-RCXT to incrementally deliver a signoff-assured result.
• Design convergence: IC Compiler, in combination with Design Compiler® topographical technology, provides the tightest correlation between synthesis and physical implementation for a highly convergent RTL-to-GDSII flow. IC Compiler is based on the industry-proven Milkyway™ database, making the design flow faster, more efficient, and more predictable. This is critical to improving turnaround time and enables designers to focus on differentiating design features instead of debugging data transfer issues.
• Multi-Corner Multi-Mode (MCMM): Concurrent MCMM-aware placement, routing, and optimization transformations dramatically reduce TAT for large, complex chips. Intelligent, optimization is driven by timing, area, power, signal integrity (SI), routability and yield cost factors that are measured concurrently across all scenarios. IC Compiler’s MCMM solution eliminates the ping-pong effects of sequential or quasi-MCMM approaches.

Figure 3. Early analysis facilitates faster design convergence

Figure 4. CAA map before and after wire spreading in IC Compiler

Cost of Design
IC Compiler allows designers to employ a variety of techniques to meet timing, power, area, routability and yield goals. This helps reduce the cost of design and increases predictability.

• DFY: IC Compiler as part of the Galaxy Design Platform offers the only complete solution available to address yield loss. IC Compiler integrates a DFT solution and fault diagnostics flow to quickly detect defect mechanisms and implement effective redesign for faster yield ramp improvement.
• Power: Power management has become a very important design issue. Advanced multi-voltage designs for wireless, mobile, and consumer applications must deliver maximum performance while minimizing power. IC Compiler and the Galaxy Design Platform have a complete low-power flow to handle extremely complex power-sensitive applications from tiny wireless to multi-million-gate graphics designs.
• Design for Test (DFT): IC Compiler as part of the Galaxy flow provides a comprehensive test automation solution that offers SoC designers the fastest and most cost-effective path to high-quality manufacturing tests and working silicon. Fully-integrated DFT MAX next-generation test compression and synthesis technology achieves high compression without affecting the test coverage, functionality, timing, or power requirements of the design.

Ease of Use
IC Compiler uses three core commands - place_opt, clock_opt, and route_opt-to deliver best out-of-the-box results. The IC Compiler GUI provides very intuitive and easy-to-use features to help designers resolve issues at all design stages. The GUI enables fast analysis, visualization, debugging and repair features.

All of these shared technologies and key advances in IC Compiler have enabled the Galaxy Design Platform to deliver the best QoR in terms of timing, area, power, routability, testability and yield as well as faster TAT and a very predictable path to first-silicon success. Today designers are using IC Compiler successfully to tape out numerous complex, high-performance and low-power designs at 130 to sub-65 nanometer (nm) geometries.

Features

• High throughput for designs in mainstream silicon technologies
• High performance for advanced silicon technologies
• Comprehensive optimization capabilities meet timing, area, power, signal integrity, routability and yield objectives
• Predictability during the implementation process
• Complete netlist-to-GDSII solution for best QoR and TTR
• Sign-off
• Highly correlated with golden signoff solutions: PrimeTime-SI and Star-RCXT
• Shares common infrastructure and technologies with PrimeTime such as Arnoldi, OCV, CRPR, CCS, common cell delay calculation and SDC constraints to ensure tight correlation
• Improves TTR by eliminating unnecessary margin
• Speeds design closure by using exact sign-off timing and extraction information

Figure 5. Via optimization in IC Compiler

Figure 6. Register grouping using power-aware -placement reduces power

• TAT
• Concurrent MCMM optimization
• Tight correlation with Design Compiler topographical technology
• Physical datapath enables dramatic improvement in productivity for datapath logic implementation and provides predictable results in timing, area, and power
• Robust crosstalk flow during all stages; detects and fixes crosstalk violations
• Power
• Support for multi-voltage designs during design planning, synthesis, placement, clock tree synthesis, routing, and chip finishing stages
• Advanced algorithms deliver high-quality dynamic and leakage optimization results
• Power-aware placement technology groups registers to reduce dynamic power
• Support for complex clock gating in clock tree synthesis
• Low-power, SI-aware CTS
• Signal electro migration analysis and repair significantly improves design reliability
• DFY
• Complete support for advanced design rules
• Cell and route-based yield optimizations
• Critical Area Analysis (CAA)
• Optimization of critical areas through wire-spreading during global route, track assignment and detailed routing
• Automated, timing driven multi-pattern via selection
• Timing-driven metal fill
• Staggered metal fill
• Model-based metal fill to correct critical systematic defects introduced by the Chemical Mechanical Polishing (CMP) process
• Tight integration with Hercules DRC/LVS checker
• Advanced routing design rule support
• Design Planning
• Complete design planning for flat chips
• Seamless hierarchical flow with JupiterXT™ hierarchical design planning solution
• Power Network Analysis (PNA), Power Network Synthesis (PNS), and power-pad synthesis capabilities
• Timing-driven automatic macro placement
• Complete multi-voltage flow with MTCMOS support
• Early analysis and feasibility exploration capabilities

Figure 7. Design before scan ordering

Figure 8. Design after scan ordering

• DFT
• Physically optimized scan chains deliver predictable timing closure
• Physical test-optimized flow with support for DFT Compiler and DFT MAX features using scanDEF interface
• QoR
• Innovative XPS optimization capabilities in timing, area, DFT, power, routability and yield ensure best QoR
• Physical datapath delivers QoR by adding controllability and predictability to the physical implementation for effective datapath management in high speed designs
• Ease of Use
• Core commands for placement, CTS, and routing
• TCL support throughout
• GUI
• Powerful features enable design analysis, visualization, debugging, and fixing
• Cross referencing between logic vs. physical analysis
• Clock tree synthesis skew and latency analysis
• Hierarchical clock tree browser
• Power Network Analysis (PNA)
• Visual maps for Worst Negative Slack (WNS)/ congestion/cell density/scan/leakage power/dynamic power/total power and more.
• Critical Area Analysis (CAA)
• CMP thickness and CMP hot spots
• Fast physical data analysis and editing
• PrimeTime-style analysis (path inspector)
• TrueVue photorealistic visualization

Figure 9. Critical path cross-highlighting enables faster debugging

Interfaces

• Library Interface
• Reads LIB synthesis library containing functionality, timing, and design rule constraints
• Reads Milkyway (MWY) physical library describing technology and cell outlines
• Reads LEF, Technology File (TF) format
• Inputs
• Verilog netlist
• -SDC, DEF, SPEF, SBPF
• -Several user-level commands are provided for specifying and modifying the floorplan
• Outputs
• Verilog netlist
• -SDC, DEF, SPEF, SBPF
• -GDSII
• User Interfaces
• TCL- or GUI-based user interface
• -All Design Compiler reports enhanced with physical information; additional reports and commands enable analyzing layout and checking consistency of libraries and input files
• Supported Platforms
• AMD64, Sparc64, Linux32 3.0, Suse 32, Suse 64