ESP-CV™

Functional Verification for Full Custom Designs

ESP-CV verifies that two different design representations are functionally equivalent. These designs may be described as Verilog behavioral models, RTL, UDP’s, gates, transistors, or SPICE netlist views.

BENEFITS

Higher Quality
ESP-CV provides fast and complete coverage, enabling you to quickly find bugs and have the confidence that the reference model is functionally identical to the transistor model.

Increased Productivity
With ESP-CV, you no longer have to derive directed and random tests or have a long delay in releasing models while you complete your verification suite.

Easy to Use
ESP-CV directly verifies the SPICE netlist, eliminating the need to manually extract transistor network into a gate-level representation.

MEMORIES ARE CHANGING

Over 50% of the total silicon real estate in today’s SOC is consumed by memories. And as designs move toward nanometer process technology, functionalities such as redundancy, ECC, BIST, pipelining, etc. are being added to these designs, resulting in significantly higher functional complexity.

With few standards and many degrees of freedom, functional verification of embedded memories has become a critical need in SOC design verification process. One of key requirement is that the behavioral reference model used for SOC full chip simulation is functionally identical to the transistor-level netlist that represents the actual implementation.

As quantity and complexity of memory designs continue to increase, while the project schedule and available resources continue to shrink, designers are faced with the challenges of delivering high quality memories, on-time, with limited resources.

HIGH COVERAGE VERIFICATION

Traditional methods used to verify memories such as SPICE simulation or cell-based formal verification have their limitations. SPICE simulation provides circuit-level accuracy but its coverage is dependent on the vector set created by the engineers and the time available for running the simulation. Likewise, cell-based formal verification may provide complete coverage but cannot accurately represent the behavior of transistor-level netlist.

ESP-CV is based on patented symbolic simulation technology that combines the power of formal methods with proven event-driven simulation technology. ESP-CV leverages symbolic simulation to a concept known as sequential equivalence checking to dramatically increase the quality of functional verification.

ESP-CV simultaneously simulates two different design representations using symbolic inputs while observing the outputs of each representation to assure equivalent responses. Instead of applying all possible combinations of binary states, ESP-CV applies a symbol that represents all possible input states. This results in coverage of 2^N possible states with only N number of symbols.

CIRCUIT-LEVEL ACCURACY

ESP-CV with CKT technology applies formal verification to the circuit-level designs, delivering easy-to-use formal verification solution with circuit-level accuracy.

Unlike other methods that require modeling of transistor-level designs to cell-based gate equivalent netlists, CKT directly verifies the functional equivalence of SPICE-level netlist against a behavioral or RTL representation of the design. ESP-CV with CKT greatly simplifies the inclusion of transistor parasitic effects in the functional model by automatically calculating the RC value based on transistor length, width, and process technology.

CONCLUSION

With increasing complexity and importance of memories in modern ICs, there is a clear need for new tools and techniques for the design and verification of embedded memory blocks. ESP-CV brings formal technology into the memory designers' hands and raises their confidence in the quality of the design while simplifying the testing process and increasing the overall verification productivity.

KEY FEATURES

Full Verilog Language
Supports any constructs from the Verilog language, including behavioral structures, such as fork, join, task, etc.

Transistor Level Verification
Transistors are native to ESP-CV and does not depend upon gate extraction or pattern matching techniques.

Asynchronous Timing
Supports asynchronous clocks, pulsed logic and self-timed logic.

No State Point Mapping
Verifies functional equivalency of designs with different structures without any dependency on isomorphic state mapping.

Extreme Capacity
Ability to verify over one billion transistor design on a single workstation.