Designware® TSMC Libraries

TSMC and Synopsys have been committed to providing SoC designers with the best tools, flows and IP for the last decade. By working together to ensure a tight integration of the TSMC Libraries and the Synopsys Galaxy platform through TSMC's Reference Flow 6.0, both companies are able to offer a complete path from RTL to GDSII.

TSMC Libraries are developed and process tuned to TSMC semiconductor technologies. Each logic and I/O cell is validated in silicon and meets the company's rigorous library quality criteria. TSMC libraries are in production, in multiple customer designs.

This unique combination of libraries, proven methodology, very high quality standards and industry-leading IP technical support will help reduce design risk and accelerate time to market.

Continuing on Synopsys' commitment to adding value to the already comprehensive DesignWare Library implementation and verification IP portfolio, all views of the TSMC 0.15, 0.13 micron, and Nexsys 90 nanometer Standard Cells and I/Os are available to DesignWare Library Licensees at no additional cost.

The libraries are packaged and delivered in two different sets of deliverables. The Front-End Views package give you access to all the views required for a complete evaluation of the libraries. The Back-End Views package includes the additional views required for tape-out. Please click on the library name below to download.

 TSMC Libraries Overview

New: Nexsys Memory Compilers for 90LP and 65LP
A complete family of memory compilers for the TCBN90LP and TCBN65LP processes developed by TSMC is now available from Synopsys. The available compilers include a Single Port SRAM, ROM as well as two port Register File compilers and followed by a Dual Port SRAM compiler.

See the TSMC Nexsys Memory Compilers page for details

TSMC Standard Cell Categories   => Click on Library name to download

TSMC Standard I/O Categories   => Click on Library name to download

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