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The Synopsys DesignWare IP solutions for SATA include a comprehensive set of synthesizable IP, verification IP, PHYs and an automated method for subsystem assembly when the Synopsys coreAssembler tool is used.
The configurable architecture of the IP, coupled with the automated assembly tool, dramatically reduces the complexity
of designing next-generation SATA-based subsystems and significantly improves overall productivity for a faster time to results.
The SATA digital cores are compliant with the SATA 2.6 specification, the SATA AHCI core is compliant with the AHCI 1.1 specification and both cores include an ARM® AMBA® 2.0 compliant subsystem interface.
Digital Core IP
- Reduce cost of deployment with silicon proven core
- Easy to integrate with configurable PHY interface to support multiple PHY vendors
- Verilog testbench simplifies writing customized tests and enables post integration testing
Verification IP
- Broadest verification IP portfolio in the industry
- Delivers 5X simulation performance improvement with VCS
- Supports proven verification methodology for SystemVerilog
- Includes example testbenches to accelerate learning and speed testbench development
For more information on DesignWare Contact Us
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