DesignWare® Memory Building Blocks - Embedded FIFO/Stack

The DesignWare FIFO and Stack components are implemented using the DesignWare embedded SRAM and memory controller components. As the memories are built from cells within the ASIC library they are high performance but you should kept them small to obtain an area efficient implementation. Some of the parameterizable features include FIFO depth, almost empty level, almost full level, level of error detection and type of reset.

DesignWare FIFO and Stack components are technology-independent and can therefore be targeted to different vendor library processes without any HDL code changes.

The DesignWare Memory Building Block components and the entire DesignWare Memory Solutions are part of the DesignWare IP library and available at no additional cost.

• Download the DesignWare Building Block Components
• FIFO Controllers
• Product Documentation

FIFO’s with Static Flags

• Synchronous (Single Clock) FIFO with Static Flags
• Synchronous (Dual Clock) FIFO with Static Flags
• Asymmetric I/O Synchronous (Single Clock) FIFO with Static Flags
• Asymmetric Synchronous (Dual Clock) FIFO with Static Flags

FIFO's with Dynamic Flags

• Synchronous (Single Clock) FIFO with Dynamic Flags
• Asymmetric I/O Synchronous (Single Clock) FIFO with Dynamic Flag

Embedded Stack

• Synchronous (Single Clock) Stack

For pricing information or to order print literature on DesignWare products, please contact the DesignWare team.