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 Memory BIST Over 30% of today's designs implements embedded memories and continuously consumes more and more die area. While embedded memory presents significant system performance and cost reduction advantages, it brings its own testing issues. Test vector style tests are not suitable for verifying embedded memory arrays because it is too costly. This is because the time spent in the manufacturing tester grows exponentially as the embedded memory die area increases. Sometimes it is impossible to create a set of vectors that can detect all possible types of memory defect.Implementing embedded memory built in self-test (BIST) can alleviate these problems. In simplistic terms, memory BIST is an on-chip utility that enables the execution of a proven set of algorithmic style verification tests directly on the memory array. These tests can be executed at the design's full operating frequency to prove the memory array operations and identify errors caused by silicon defects. The DesignWare Memory BIST MacroCell, DW_rambist, is a configurable, fully synthesizable solution formemory built-in self test of embedded SRAM memory structures. DW_rambist increases overall product quality by ensuring fault coverage of embedded memory defects through built-in algorithmic testing. In order to reduce test time and maximize utilization of embedded test resources, DW_rambist executes tests in parallel with a shared BIST controller. Four industry-standard SRAM BIST algorithms are selectable at runtime: March LR, March C-, MATS++ and a retention test using a pause-polling mechanism.
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