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DesignWare Technical Bulletin
ISSUE #: Q1-08
INSIDE THIS ISSUE
What's New in DW IP
Technical Articles
Featured Whitepapers
Training and Events
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Welcome to the DesignWare Technical Bulletin
This quarterly newsletter brings you up-to-date on recent DesignWare IP news, from product announcements to upcoming seminars.

What's New

WHAT'S NEW IN DESIGNWARE IP
DW Arrow Synopsys Enhances DesignWare IP for DDR2 and DDR3
DW Arrow DesignWare System-Level Library - It's like hardware, only better!
DW Arrow Latest DesignWare IP SolvNet Articles
DW Arrow Update to Six DesignWare Building Block IP Application Notes
DW Arrow KeyEye Communications Saves Two Man Years of Effort with DesignWare PHY IP

Videos

DW Arrow Take a virtual tour of the Synopsys engineering lab to see how we verify the DesignWare USB 2.0 PHY IP and get a brief introduction on the key features. See how Synopsys invests in hundreds of test chips to ensure high quality IP.

News Releases and Articles

DW Arrow Synopsys. New DesignWare IP Significantly Simplifies Transition to PCI Express
DW Arrow Synopsys Enters Embedded Memory Market With Highly Differentiated IP
DW Arrow Synopsys Expands Leading USB IP Portfolio With New IP for Link Power Management and High Speed Inter-Chip Standards
DW Arrow Synopsys' DesignWare DDR Protocol Controller IP Integrated Into Arteris' Network-On-Chip Interconnect Solution
DW Arrow Low Power Design for Analog/Mixed-Signal IP
Technical Articles

TECHNICAL ARTICLES
DW Arrow USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
Learn how the new USB HSIC IP can simplify your USB connection by removing the cables and connectors. Understand how the digital controller and PHY IP enable you to significantly lower area and power.
DW Arrow Know Your Protocol: A Verification IP Perspective
See why having basic knowledge of the IP you’re using is imperative for accelerating design and verification schedules. This article, discusses how the selection and integration of Verification IP plays a significant role in your overall verification plan.
DW Arrow Building a Bridge from PCI Express to AMBA 3 AXI On-Chip Bus
PCI Express is the next generation interface for computer expansion and graphics cards while AMBA is the industry standard that enables high reusability and connectivity. In this article, learn the process of building a bridge from PCIe to an AMBA 3 AXI on-chip bus.
DW Arrow DDR2/3 SDRAM Controller Options: Protocol or Memory Controller
Understand the functionality required for your next design’s SDRAM controller. This article discusses the differences between a full-featured, high bandwidth SDRAM memory controller and a lean, efficient SDRAM protocol controller.
Technical Articles

FEATURED WHITEPAPERS
DW Arrow DDR SDRAM: A Low Cost, Yet Increasingly Complex Off-Chip Memory Solution for SoCs
This whitepaper provides a brief history of the SDRAM, discusses the design considerations for implementing a DDRn controller and PHY, and describes how a complete IP solution can help speed time-to-market and reduce costs.
DW Arrow Understanding the Fundamentals of PCI Express
This whitepaper will provide you with a broad understanding of the PCI Express® protocol and discuss the design challenges associated with implementing the PCI Express controller, PHY IP and verification IP into high-performance SoC designs.
Training

TRAINING AND EVENTS
DW Arrow Experts on the Road China: Register Now!
April 7, 2008 – Beijing | April 9, 2008 – Shanghai | April 11, 2008 – Shenzhen