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What's New in DesignWare IP?New IP Available in DesignWare Library: New IP Available Separately: New IP Resources:
Synopsys has expanded its portfolio of DesignWare® Library intellectual property (IP) with the release of verification IP for the Open Core Protocol (OCP) interface. OCP is a common standard IP core interface, or socket, that facilitates "plug and play" system-on-chip (SoC) design. Synopsys has developed verification IP for the OCP interface in response to customer demand for a means to verify OCP-based systems and cores using the DesignWare and VCS® Verification Libraries. The DesignWare Library and VCS Verification Library include verification IP for AMBA® 2.0, AMBA 3 AXI, PCI Express® USB, Serial ATA, Ethernet, I2C, serial I/O and memories. The addition of OCP 2.1 to the library portfolio enables the verification of OCP cores, OCP systems and mixed OCP/AMBA systems with their external interfaces. OCP verification IP provides 100 percent coverage as defined in section 4 of the Synopsys document, "OCP 2.0/2.1 Compliance Checks." It is compliant with the popular VMM methodology, as defined in the Verification Methodology Manual for SystemVerilog, enabling easy integration with constrained-random, coverage-driven environments. Verification IP for the OCP interface supports Verilog and VHDL testbenches and all popular simulators, and enables up to five times faster verification when used with the VCS comprehensive functional verification solution. The DW_axi_x2p is an AXI-to-APB bridge and fabric that seamlessly connects an AMBA 3 AXI compliant interconnect to an APB 3 compliant interconnect. The DW_axi_x2p bridge translates AXI transactions into APB transfers, enables flexible address and data port configurations, supports up to sixteen APB 2 or APB 3 slaves, supports a single clock or two asynchronous clock domains and buffers AXI transactions. The DW_axi_x2p is a configurable component, allowing the IP integrator to optimize the IP to suit specific design requirements. In order to generate slave IDs, current interconnects on the market append the master number to the master ID bus. In order to allow the correct routing of the response to the master, AXI protocol dictates a slave ID width that is a function of the master ID width and the number of master ports associated with the interconnect. However, there is an inherent paradox if two or more interconnects are connected together, and masters on more than one interconnect are accessing slaves in the system. The enhanced DesignWare Interconnect Fabric for AMBA 3 AXI, DW_axi addresses this issue and ensures correct routing of responses to the masters. A complete set of TSMC Nexsys Standard Cells for the TSMC 65-nm GPlus process is now available to all DesignWare Library licensees. Available for Nominal, Low or High Vt, the libraries are optimized for low power design and enable power and performance tradeoffs. Designed by TSMC in conjunction with TSMC's process technology team, the standard cells fully comply with TSMC's Design For Manufacturing rules. These new libraries provide support for multi-voltage island and coarse grain MTCMOS implementation. In addition, new Standard Cells libraries with support for multi-voltage island and coarse grain MTCMOS implementation are available for TSMC 65-nm Low Power processes. These libraries are also available in three Vt Variations (Nominal, Low and High). These libraries complement the offering already available for TSMC 90-nm, 0.13-µm and 0.15-µm.
The new PCIe-AHB Bridge is part of the complete DesignWare IP solution for PCI Express, including digital cores, mixed-signal PHY IP and verification IP. The bridge enables designers who use the AMBA 2.0 AHB on-chip bus to easily add PCI Express external connectivity to their AMBA 2.0 AHB SoC devices. The DesignWare Bridge for PCI Express to AMBA 2.0 AHB can be used in conjunction with DesignWare IP solutions for AMBA 2.0 AHB, including synthesizable IP, verification IP and automated assembly using the Synopsys coreAssembler tool. The DesignWare IP solutions for AMBA 2.0 AHB are available today for no additional charge to DesignWare Library licensees. Synopsys and First Silicon Solutions (FS2), a division of MIPS Technologies, have collaborated to develop a high-performance Sitka evaluation and development platform for DesignWare PCI Express IP. The Sitka board functions as a standard PCIe add-in card with support for up to eight PCIe lanes (each lane is a 2.5 Gbps communication channel). With this new platform, designers can test and debug their system-on-chip (SoC) designs using the DesignWare PCIe IP while performing interoperability testing between their SoC design and a PCIe PHY. Designers using the Sitka board to prototype SoCs can reduce their design risk, cut development time and enable predictable success in their complex SoCs. With the Sitka board, designers can prototype large designs by synthesizing their SoCs into two large on-board Xilinx Virtex™ 4 FPGAs. These two FPGAs are interconnected through 272 I/O pins and can be configured for operation at up to 1 Gbps point-to-point, providing high throughput data transfers or sets of unidirectional channels. The FPGAs are configured via the on-board ROM. The ROM can hold multiple FPGA configurations, allowing the designer to test design variations and switch between different PHYs and the Xilinx Rocket I/O™. Synopsys has used the Sitka board for compliance testing of the combined DesignWare PCI Express digital cores and DesignWare PCI Express PHY at PCI Special Interest Group (PCI-SIG®) Compliance Workshops. For design development and prototyping, the Sitka board provides multiple options for the PHY interface. For initial prototyping, designers can use the built-in Xilinx Rocket I/O SERDES, connected directly to the Sitka PCIe interface. For more extensive PCIe and PHY compatibility testing, designers can use a PCIe PIPE-compliant PHY and connect through the standard PIPE-C-compliant expansion connector. For DesignWare PCIe digital IP evaluations, Synopsys provides an FPGA configuration that allows the Sitka board to be used as a PCI Express-based 10/100 Ethernet adapter. Synopsys has expanded its DesignWare mixed-signal intellectual property portfolio with the release of connectivity IP for Semiconductor Manufacturing International Corporation's (SMIC's) 130-nm technology. The mixed-signal PHY IP supports USB, PCIe, SATA and XAU protocols. These PHYs are highly complex, process-tuned analog interfaces for today's high-volume, highly integrated mobile terminals, home entertainment, computing, storage and networking applications. Additionally, high-performance DesignWare memory interface I/Os, such as DDR2 and mobile DDR, are available on SMIC's 130-nm process.
Synopsys has unveiled IP Bookcase, the definitive online source for information about products, issues, and trends shaping the IP industry. IP Bookcase is organized in a user - friendly format to save time and provide the information you need for smart purchasing decisions. Whitepaper topics range from PCI Express to Wireless USB, SATA, and more. New whitepapers will be featured each month. Bookmark the site for easy reference. Documentation such as databooks, installation guides, and release notes for the DesignWare Cores product line can be downloaded from the web for licensed users. The following new Solvnet articles have been developed to assist our users in learning more about DesignWare Verification IP (VIP) and its features:
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