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What's New in DesignWare IP?New IP Available in DesignWare Library: New IP Available Separately: New IP Resources:
Synopsys announces the industry’s first Verification IP for SystemVerilog with methodology support. DesignWare® Verification IP (VIP) now supports the constrained-random, coverage-driven methodology defined in the Verification Methodology Manual (VMM) for SystemVerilog and is an integral part of the Synopsys Discovery™ Platform. When combined with native testbench in VCS®, DesignWare Verification IP delivers up to 5x improvement in runtime performance. Verification engineers who use SystemVerilog for testbench development now have access to a broad and proven portfolio of standards-based VIP to dramatically speed testbench development time and achieve functional coverage goals faster. Highlights include:
Press Release
The version 1.02a release includes enhancements to the DesignWare Synthesizable IP for the AMBA 3 AXI interconnect fabric, DW_axi. It also introduces a new component, the register slice, DW_axi_rs, which implements the pipelining of the AMBA 3 AXI protocol channels to facilitate timing closure. This is essential in designs where the register-to-register timing between signaling on the AMBA 3 AXI interfaces are critical paths. Full Article
Tower Semiconductor released an updated version (2005.12) of its 0.18μm Standard Cell library (FS120), which was re-characterized with latest version of SPICE models. An optimized flow was used to improve timing and power characterization of the standard cell library in order to achieve better correlation with actual process results. The FAST Silicon Standard Cell Library has a complete set of cell functionalities with drive strengths that are optimized for industry standard design flows and the Synopsys Galaxy™ platform. The main changes enable improved design accuracy through optimized delay and slope tables, while providing better support for current tools. The directory structure of the library was slightly changed to better support current version of EDA tools. Tower highly recommends all it's customers to use this updated library for the design of new products. The new version of the Tower standard cell library is available to all DesignWare Library licensees at no additional cost.
The new DesignWare USB 2.0 nanoPHY IP is an addition to its existing DesignWare USB 2.0 physical layer (PHY) product line. The new mixed-signal PHY IP builds on Synopsys' three years of leadership in successfully providing USB 2.0 PHY intellectual property (IP) in more than two dozen process node and configuration combinations. The new DesignWare USB 2.0 nanoPHY IP is tailored specifically for low-power consumption, small area, and high yield. It targets designers of mobile, high-volume consumer applications such as next generation handheld game machines, feature-rich smart phones, digital cameras, and portable audio and video players. Press Release
Synopsys now distributes low-power optimized 90LP TSMC Nexsys Memory Compilers, enabling customers to take advantage of silicon proven, DFM compliant and TSMC process optimized compilers. The Memory Compilers available today include: Single port SRAM with redundancy, Single port SRAM without redundancy, ROM and 2 port register file with redundancy. TSMC and Synopsys plans to make additional the memory compilers available in the near future. Product Information
The DesignWare Mixed-Signal I/O Libraries are now available in the TSMC 130nm LV, 3.3V I/O oxide and TSMC 130nm LVOD, 3.3V I/O oxide process technologies. This new release expands Synopsys coverage of the TSMC 130nm process node by providing I/O solutions for customers requiring higher performance or lower power than that of the Generic (G) process. The DesignWare Mixed-Signal I/O Libraries combine proven interface design techniques, rigorous system interconnect validation, and documented integration and system engineering support in a suite of standards-based I/O libraries to meet today's interface IP requirements.
Synopsys breaks new ground by taking customers behind the scenes for interviews and discussions on IP through podcasting, the fastest growing communication medium. Synopsys’ IP Radio, a new podcast series, gives you the ability to listen to people who are passionate about IP and the chips they go into. The inaugural edition eavesdrops on an executive-level discussion between Mike Keating, Synopsys Fellow, John Chilton, Sr. Vice President and General Manager and Guri Stark, Vice President of Marketing as they discuss the past, present and future of IP and how it will redefine the semiconductor industry. With Synopsys IP Radio, you can conveniently listen to audio programming anywhere and at any time. Documentation such as databooks, installation guides, and release notes for the DesignWare Cores product line can now be downloaded from the web for licensed customers. Four new Solvnet articles have been developed to assist our customers in learning more about DesignWare Verification IP (VIP) and its features:
016925 Using reset_model command with VIP Models |
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