HELPING YOU DESIGN THE CHIP INSIDE
Products and Solutions
---------- SOLUTIONS ----------
Eclypse Low Power Solution
Galaxy Design Platform
• Design for Low Power
• Design for Test
• Design for Yield
• RTL Synthesis
• Physical Implementation
• Sign-Off
• Liberty CCS
• SDC
• Milkyway
Discovery Verification Platform
• Analysis and Debug Tools
• Low-Power Verification
• System Analysis & Design
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• Functional Equivalence Checking
• Mixed-Signal
• Languages
Intellectual Property (IP)
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Design for Manufacturing
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• Mask Data Preparation
• Lithography Verification
• TCAD
• Manufacturing Yield Management
Professional Services
• Tool and Methodology Deployment
• Pilot Design Environment
• Flow Optimization
• Implementation
• Verification Consulting
• Concept to Parts
• Core Hardening
---------- PRODUCTS ----------
BSD Compiler: Test synthesis
Cadabra: Cell creation
Calibration Library
CATS: Mask data preparation
Circuit Explorer: Analysis & Optimization
coreAssembler
coreBuilder
coreConsultant
CosmosLE: Layout design environment
CosmosScope: Waveform analysis
CosmosSE: Schem. design environment
DC Ultra: RTL synthesis
Design Analyzer: RTL synthesis
Design Compiler: RTL synthesis
DesignWare: Design & verif. IP
DesignWare Virtual Platforms
DFT Compiler MAX
DFT Compiler: Test synthesis
DSSA Sentry
Enterprise: Layout editor
ESP: Transistor-level Equivalence Checking
Formality: Funct. equiv. checking
Hercules: Physical verification
HSIM
HSPICE: Accurate circuit simulation
IC Compiler
IC Workbench
Innovator: SoC / system modeling
JupiterXT: Design planning
Leda: RTL checker
Library Compiler: Library compilation
Liberty NCX: CCS Characterization
Magellan: RTL formal verification
Memory Solution
Milkyway: Design database
MVRC
MVSIM
NanoChar: 90 nanometer & below characterization
NanoSim: Fast circuit simulation
NanoTime
Odyssey Defect/Odyssey YMS
Paramos
Pilot Design Environment
Pioneer-NTB: SystemVerilog testbench automation
Power Compiler: Power optimization
PrimePower: Power analysis
PrimeRail
PrimeTime PX
PrimeTime: Static timing analysis
PrimeTime SI: Signal integrity analysis
PrimeYield Tool Suite
Proteus OPC
PSM-Create & PSM-Check
Raphael
Raphael NXT
Recipe Manager and Editor (RME)
Saber: Multi-tech. simulation
Scirocco: VHDL simulation
Seismos
Sentaurus Device
Sentaurus Lithography
Sentaurus Process
Sentaurus Structure Editor
Sentaurus TFM
Sentaurus Topography
Sentaurus Workbench
SiVL-LRC: Lithography verification
SpiceCheck
SpiceExplorer
Star-RCXT: Full-chip RC extraction
Star-RCXT VX
Star-SimXT: Fast circuit simulation
System Studio: DSP algorithm design
Taurus-Medici
Taurus-TSuprem4
TetraMAX: ATPG
VCS: Comprehensive RTL Verification
VCS MX: Mixed-HDL simulation
Vera: Testbench automation
WaveView Analyzer
DESIGN IMPLEMENTATION
VERIFICATION
INTELLECTUAL PROPERTY
DFM/TCAD
DESIGN SERVICES
ISSUE #: Q2-08
INSIDE THIS ISSUE
What's New in DW IP
Technical Articles
Featured Whitepapers
Training and Events
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The following new articles about DesignWare products were published on SolvNet during Q1
Information on nbw implementation
DW_ahb_dmac Support for Defined-Length Bursts
Using Decimals in Clock Periods for Simulation with DesignWare VIP
URMI error encountered while simulating DesignWare IIP
PCI Express 2.0: Comparing 2.5-Gbps Solutions Versus 5.0-Gbps Solutions
How to Change the Memory BAR Size in PCIe-AHB Cores
DWC SATA Host PIO programming guidelines
DesignWare USB 2.0 OTG PHY Hard Macro Test Interface
PCI Express Cores: How can you parameterize 2 separate instances of the core?
DesignWare USB 2.0 Device Subsystem IP: Coming out suspend during soft-disconnect
DesignWare USB 1.1/2.0 Device Subsystem IP: Overrun condition in Buffer-Filled mode
Synthesiszing DesignWare DW_arb_rr arbiter
Functional Issue with DesignWare Sequential Divider DW_div_seq
Synthesizing DesignWare Datapath Functions
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