DesignWare Technical Bulletin Archives

• Synopsys Enhances DesignWare IP for DDR2 and DDR3 (Q1-08)
• DesignWare System-Level Library - It's like hardware, only better! (Q1-08)
• Latest DesignWare IP SolvNet Articles (Q1-08)
• Update to Six DesignWare Building Block IP Application Notes (Q1-08)
• KeyEye Communications Saves Two Man Years of Effort with DesignWare PHY IP (Q1-08)
• Synopsys. New DesignWare IP Significantly Simplifies Transition to PCI Express (Q1-08)
• Synopsys Enters Embedded Memory Market With Highly Differentiated IP (Q1-08)
• Synopsys Expands Leading USB IP Portfolio With New IP for Link Power Management and High Speed Inter-Chip Standards (Q1-08)
• Synopsys' DesignWare DDR Protocol Controller IP Integrated Into Arteris' Network-On-Chip Interconnect Solution (Q1-08)
• Low Power Design for Analog/Mixed-Signal IP (Q1-08)
• USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it? (Q1-08)
• Know Your Protocol: A Verification IP Perspective (Q1-08)
• Building a Bridge from PCI Express to AMBA 3 AXI On-Chip Bus (Q1-08)
• DDR2/3 SDRAM Controller Options: Protocol or Memory Controller (Q1-08)
• DDR SDRAM: A Low Cost, Yet Increasingly Complex Off-Chip Memory Solution for SoCs (Q1-08)
• Understanding the Fundamentals of PCI Express (Q1-08)
• Synopsys DesignWare USB 2.0 nanoPHY and PCI Express PHY IP Achieve Compliance in SMIC's 130-nm Process Technology (Q4-07)
• Synopsys DesignWare IP for 5.0 Gbps PCI Express Enables First-Pass Silicon Success for PMC-Sierra's High Performance SoC (Q4-07)
• Synopsys Selected to Develop 45-Nanometer USB PHY IP for IBM Foundry Process (Q4-07)
• Synopsys' DesignWare IP Passes Certified Wireless USB Testing from USB-IF (Q4-07)
• New Datapath and Building Block IP in 2007.12 Release of the DesignWare Library (Q4-07)
• Designers Highlight Challenges of High-Speed I/O: ICCAD Conference Coverage (Q4-07)
• Low Power Methodology Demystified: Insights into the LPMM (Q4-07)
• New SolvNet Articles for DesignWare IP for AMBA (Q4-07)
• USB IP Blog: Covering the Latest Trends and Topics in USB IP (Q4-07)
• Mixed-Signal IP Blog: Discussing all topics related to PHY IP such as latest trends and challenges (Q4-07)
• Inside Protocol Verification Blog: Providing insights on issues, new features and advanced methodologies related to the verification of bus protocols (Q4-07)
• Proven DesignWare IP for PCI Express Helps Stretch Reduces Integration Risk and Speed Time-to-Market (Q4-07)
• DesignWare Verification IP with the VMM Methodology Shortens Testbench Development Time for DSP Group (Q4-07)
• Leading DesignWare IP for PCI Express Helps AGEIA Achieve High Performance Goals for Game Physics Processor (Q4-07)
• Silicon-Proven DesignWare USB 2.0 PHY IP Lowers Integration Risk and Enables First Pass Silicon Success for Hisilicon Technologies (Q4-07)
• Understanding the DesignWare USB 2.0 Host Controller's New Feature for OHCI Clocks (Q4-07)
• Tradeoffs Between Combinational and Sequential Dividers (Q4-07)
• PCI Express 2.0: Comparing 2.5-Gbps Solutions Versus 5.0-Gbps (Q4-07)
• Implementing Floating-Point IP for the Right Accuracy and Quality of Results (Q4-07)
• Integration Issues and Solutions for USB Enabled Designs (Q4-07)
• Life Begins at 65 - Unless You are Mixed-Signal? (Q4-07)
• The Good? The Bad? The Ugly? IP Perspectives from Vendor to SoC Integrator (Q4-07)
• Synopsys Announces DesignWare System-Level Library (Q3-07)
• Synopsys Completes Acquisition of MOSAID Semiconductor IP Assets (Q3-07)
• Synopsys Agrees to Acquire MOSAID Semiconductor IP Assets (Q3-07)
• Synopsys Teams With UMC to Port Mixed-Signal Connectivity IP to 90- and 65-Nanometer Process Technologies (Q3-07)
• Synopsys Enhances DesignWare Synthesizable IP for AMBA 3 AXI Interconnect Fabric (Q3-07)
• Synopsys DesignWare Verification IP Supports PCI Express Gen II and PIPE 1.87 Specifications (Q3-07)
• Tarari Speeds Time to Market by Three Months with DesignWare VIP for PCI Express (Q3-07)
• Open-Silicon Saves Three Months on Schedule with High Quality IP (Q3-07)
• High Quality, Great Support and Latest Feature Set Made DesignWare IP the Right Choice for Cavium Networks (Q3-07)
• DesignWare IP for PCI Express Helps Reduce Power Consumption and Lower Area for Ralink Chipset (Q3-07)
• Combination of Tools, IP and Services Help Teradici Achieve First Silicon Success (Q3-07)
• iVivity Lowers Power and Area with DesignWare IP (Q3-07)
• DesignWare IP for PCI Express Helps SiCortex Enable First Pass Silicon Success (Q3-07)
• Accent, Matrox and Synopsys Discuss IP -- Is it The Good, The Bad, or The Ugly. Perspectives from the SoC Designer, Integrator and Vendor (Q3-07)
• Intel and Synopsys Discuss The Latest in PCI Express Gen II (Q3-07)
• A Cheat Sheet for the DesignWare Solutions for AMBA IP (Q3-07)
• A Guide to Understanding the Latest Enhancements for DesignWare Synthesizable IP for AMBA 3 AXI Interconnect Fabric (Q3-07)
• Get the Latest Product Information on DesignWare IP Through myDesignWare.com (Q3-07)
• Extending Open Core Protocol (OCP) Functionality with VMM: Implementing a Slave Memory for Verification IP (Q3-07)
• Understanding the Fundamentals of PCI Express (Q3-07)
• How a Complete IP Solution Speeds Time-to-Market and Reduces Risk for 10 Gigabit Ethernet Applications (Q3-07)
• DDR SDRAM: A Low Cost, Yet Increasingly Complex Off-Chip Memory Solution for SoCs (Q3-07)
• The Complete USB 2.0 IP Solution: Understanding Today's Design Considerations and Managing Tomorrow's Challenges (Q3-07)
• High-Speed Serial Interface Testing: Solving the Analog Test Problem With a Fast and Accurate Digital Solution (Q3-07)
• Connecting to DDR2: Mitigating High-Speed Challenges in SoC Designs (Q3-07)
• Synopsys Announces the Industry's First Comprehensive SATA AHCI IP Solution (Q2-07)
• Synopsys Achieves Two IP Firsts: 65-nm PCIe and 90-nm USB Compliance Utilizing Common Platform Technologies (Q2-07)
• Synopsys Switch IP for PCI Express Passes PCI-SIG Compliance Testing (Q2-07)
• Synopsys Unveils Industry's First Certified Hi-Speed USB 'On-The-Go' nanoPHY IP for TSMC's 65-nanometer Process (Q2-07)
• Synopsys Enhances DesignWare Synthesizable IP for AMBA 2 and AMBA 3 AXI Protocols (Q2-07)
• Synopsys Releases Wireless USB WHCI Host and Dual-Role Device IP Based on the Certified Wireless USB Specification From USB-IF (Q2-07)
• OCP-IP Standardizes on Synopsys' DesignWare Verification IP for OCP-IP's Corecreator Verification Toolset (Q2-07)
• New Release of DesignWare Verification IP for I2C is now available for download (Q2-07)
• Synopsys DesignWare Ethernet VIP saves two months time to market on Commex chip (Q2-07)
• Latest Update to DesignWare Documentation and STARS-on-the-web (Q2-07)
• Pipelining with DesignWare Building Block IP (Q2-07)
• Overview of 2007.04a Release of DesignWare Synthesizable IP for AMBA 2.0 and AMBA 3 AXI (Q2-07)
• An Introduction to Synopsys' New SATA AHCI Digital Core Solution (Q2-07)
• New Download and Installation Process for DesignWare Synthesizable IP for AMBA 2.0 and AMBA 3 AXI (Q2-07)
• DDR2 SNUG Tutorial: DDR2-533 and Beyond with DesignWare Memory Interface IP (Q2-07)
• Implementing Physical Layer Connectivity IP in Deep Sub-Micron Technologies (Q2-07)
• Benefits and Applications of the Wireless USB WHCI Host and Dual-Role Device (Q2-07)
• 2007.03 DesignWare Library Datapath and Building Block IP - DesignWare® Library introduces 19 new Building Block IPs in the 2007.03 release (Q1-07)
• DesignWare Verification IP for OCP 2.1 (Open Core Protocol) - Now at Production Release and Ready for Download (Q1-07)
• DesignWare Verification IP adds support for SystemVerilog and VMM in VCS-MX (Q1-07)
• DesignWare Verification IP adds native performance in VCS for Verilog-based Testbenches (Q1-07)
• Updates to TSMC Nexsys Libraries for the 65-nm and 90-nm Process Technology (Q1-07)
• DesignWare DDR2 Memory Interface - a complete system-level IP interface solution for high-performance DDR2 SDRAM memory subsystems (Q1-07)
• New SolvNet articles on DW IIP, VIP and DW Cores featuring AMBA, PCI Express and more (Q1-07)
• IP and TCP/UDP Checksum Offload Functionality and its Support in Synopsys' DesignWare Ethernet MAC 10/100/1000 - Universal Core (Q1-07)
• DesignWare Introduces Port Monitor Verification IP for the AMBA 3 AXI Protocol (Q1-07)
• Formality Equivalence Checker Provides Industry's Best Arithmetic Verification Coverage (Q1-07)
• High Performance Connectivity IP - Avoiding Pitfalls When Selecting An IP Vendor (Q1-07)
• Synopsys Wins OCP-IP Outstanding Contributor of the Year Award (Q1-07)
• Synopsys Wins analogZONE's 'Best Connectivity IP' Award for its PCI Express®, SATA and XAUI PHYs (Q1-07)
• Synopsys IP for PCI Express 2.0 (GEN II) Passes PCI-SIG Compliance - First IP Provider to Pass PCI-SIG Compliance Testing with Complete PHY and Digital Controller Solution (Q1-07)
• Synopsys' Designware IP for PCI Express Supports NXP Semiconductors' PXPIPE PHY Interface - Collaboration Delivers Proven Digital Controller IP and External PHY Solution (Q1-07)
• Mixed-Signal IP Podcast: Life Begins at 65nm - The challenges of implementing complex systems in silicon at 65nm (Q1-07)
• SLS Demo On Demand: Early Software Development Using Synopsys Virtual Platforms (Q1-07)
• SNUG San Jose: Technical sessions & tutorials on MSIP, AMBA, DDR2 and more! (Q1-07)
• What's New in DesignWare IP? (Nov 2006)
• DesignWare Introduces the AMBA 3 AXI to APB3 Bridge and Fabric Synthesizable IP (Nov 2006)
• DesignWare Introduces Bi-Directional Command Support in Interconnect Fabric for AMBA 3 AXI (Nov 2006)
• Using DW_ahb_dmac in an AXI Subsystem (Nov 2006)
• Connecting an AMBA 2.0 AHB Subsystem to an AMBA 3 AXI Subystem (Nov 2006)
• Accelerating Functional Closure: Synopsys Verification Solutions (Nov 2006)
• Performance of Different Multipliers in the DesignWare Building Block IP (Nov 2006)
• Reducing AMBA-based SoC Design Time More Than 50% Using coreAssembler (Nov 2006)
• What's New in DesignWare IP? (Jul 2006)
• Webcast: Building a Bridge to PCI Express: A Case Study Using AXI (Jul 2006)
• On-demand demo: Accelerate AMBA 3 AXI Design Verification with DesignWare (Jul 2006)
• Integrating a PCI Express® Digital IP Core into a Gigabit Ethernet Controller (Jul 2006)
• Beyond DDR2 400: Physical Implementation Challenges in SoC Design (Jul 2006)
• High Speed Serial Interconnects - What to Look for When Selecting an IP Vendor (Jul 2006)
• Advanced Stimulus Generation with DesignWare® Verification IP and VMM for SystemVerilog (Jul 2006)
• XGXS-PCS IP - PCS for 10G Ethernet eXtender Sublayer (Jul 2006)
• What's New in 2006.06 DesignWare Library Datapath and Building Block IP (Jul 2006)
• New Floating Point Components in DesignWare Library (Jul 2006)
• coreTools 2006.03 is now available (Jul 2006)
• What's New in DesignWare IP? (Apr 2006)
• PCI Express IP Online Demo: A Quick Tour (Apr 2006)
• Verification IP Online Demo: Updated with SystemVerilog (Apr 2006)
• Low Power USB 2.0 PHY IP for Consumer Applications (Apr 2006)
• Favorable Economics Will Drive Rapid Adoption of Certified Wireless USB (Apr 2006)
• How Silicon IP will Change the Semiconductor Landscape (Apr 2006)
• Deciding on FIFO Sizes When Implementing DW Digital Cores (Apr 2006)
• What's New in DesignWare IP? (Jan 2006)
• Building the Total Quality Experience in IP (Jan 2006)
• Advanced Techniques for Robust Testbench Development (Jan 2006)
• Enabling Rapid Adoption of the AMBA 3 AXI Protocol-Based Designs (Jan 2006)
• Connecting AMBA 2.0 AHB Slave to AMBA 3 AXI Subsystem (Jan 2006)
• Creating an AMBA 3 AXI to AMBA 2.0 APB Bridge (Jan 2006)
• Latest Release: DesignWare Ethernet MAC Universal Cores (Jan 2006)
• Performance of Different Dividers & Square Root Components (Jan 2006)
• What's New in DesignWare IP? (Oct 2005)
• Achieving Compliance and Interoperability for Your PCI Express Design (Oct 2005)
• High-Speed Serial Interconnects - Free Live Webcast (Oct 2005)
• What's New in DesignWare IP? (Jul 2005)
• Coding Guidelines for Datapath Synthesis (Jul 2005)
• Selecting PCI Express IP for Your Designs (Jul 2005)
• Five Vital Steps to a Robust Testbench with DW Verification IP (Jul 2005)
• What's New in DesignWare IP? (May 2005)
• Quickly Create AMBA-based Designs with DesignWare Connect (May 2005)
• Designing Using the AMBA 3 AXI Protocol (May 2005)
• What's New in DesignWare IP? (Mar 2005)
• Getting Better Synthesis Results w/ DW Library (Mar 2005)
• DW Verification IP Delivers Performance Benefits (Mar 2005)
• Using Vera & Constrained Random to Improve Quality (Mar 2005)
• Verification IP Qualification & Usage Methodology (Mar 2005)
• What's New in DesignWare IP? (Dec 2004)
• DesignWare Library License Change (Dec 2004)
• DesignWare USB OTG VIP - Model Configuration Basics (Dec 2004)
• USB OTG PHY Enables High Quality, Cost Effective Connectivity (Dec 2004)