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Overview
The DesignWare® XAUI PHY intellectual property (IP) is designed for use in any networking or high-end computing system-on-chip (SoC) solutions.
Designed for the latest high speed backplanes, the XAUI PHY supports the 10 Gigabit Ethernet standards that are commonly used in high speed communications applications.
Based on Synopsys' proven high-speed SERDES technology, the DesignWare XAUI PHY provides a cost effective and extremely low power solution that is designed to meet the needs of today's XAUI designs.
To handle increasing communication system speeds, the XAUI standard was designed to take a 10 Gbps serial stream and divided into four 2.5Gbps serial streams that run over copper traces and chip to chip connections using 8B10B coding at 3.125Gbaud.
By taking advantage of copper links, higher performance communications applications can be cost effectively deployed.
The XAUI PHY integrates high-speed mixed-signal custom CMOS circuitry compliant with the XAUI base specification.
While extremely low in power consumption and area requirements, Synopsys' XAUI PHY substantially exceeds the electrical specifications in such key performance areas as jitter and receive sensitivity
Highlights
- Supports a wide range of configurations including 1.0v & 1.2v core supplies and 2.5v & 3.3v I/O supplies
- Supports IEEE 802.3ae
- Supports popular 90 nm and 130 nm processes
- Excellent performance margin and receiver sensitivity
- On board scope and diagnostics for fast system verification
- Supports popular 90nm and 130nm processes
- Extremely low power consumption per lane resulting in significant savings
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