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Overview
The DesignWare® Cores Hi-Speed USB On-The-Go (HS OTG) Controller Subsystem provides designers high-quality USB IP for the most demanding USB 2.0 peripherals.
Based on Synopsys' success in building and deploying Hi-Speed USB 2.0 Host, Device and PHY designs in over 100 design wins,
the DesignWare HS OTG Subsystem incorporates all Synopsys learning to date in Reuse Methodology, Constrained Random Verification,
and USB PHY interoperability to deliver flexible, quality IP in Verilog source.
The DesignWare HS OTG Subsystem performs as a standard Hi-Speed, Dual-Role Device (DRD), operating as either a USB 2.0 Hi-Speed compliant peripheral, or Hi-Speed USB 2.0 host.
For example, when HS OTG is implemented in a PDA, the PDA can synchronize with a PC. The PDA can also act as the host printing pictures and documents directly to a USB printer without the aid of a PC.
Additional applications include mobile phones, MP3 players, digital cameras, set-top boxes, scanners and fax machines.
The DesignWare USB HS OTG Subsystem delivers a flexible, low gate count USB controller capable of OTG, host and device functions.
Highlights
- Hardware state machines maximize performance and minimize CPU interrupts
- Flexible parameters enable easy integration into low and high-latency systems
- Transfer or transaction-based processing of USB data is based on system requirements
- Configurable data buffering options fine-tune performance/area trade-offs
- Buffer and descriptor pre-fetching maximizes host throughput
- Firmware-selectable endpoint configurations enable post-silicon application changes and the flexibility of one-chip design for multiple applications
- Quality IP is tested through extensive Constrained Random Verification
- AMBA High-Performance Bus (AHB) interface enables rapid integration into ARM-based designs
- UTMI+ Level 3 enables rapid integration with compatible PHYs
- Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps) operation is compliant to the USB OTG Supplement
- Supports all OTG features, including Host Negotiation Protocol and Session Request Protocol
- Verilog Source RTL
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