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Overview
The DesignWare® Cores SATA Host intellectual property (IP) is designed for use in system-on-chip (SoC) solutions.
The IP uses the popular AHB standard for a host interface and configurable PHY/link interface to support a number of industry PHYs.
Synopsys provides a large set of parameters to enable the IP's integration in systems with different requirements.
By leveraging these parameters, designers can optimize gate count and reduce integration time.
Serial Advanced Technology Attachment (SATA 1.0a and II) is designed to handle high-speed storage in desktops, mobile and consumer electronics, servers, and networked-storage environments.
SATA is a low-cost solution with improved speed and bandwidth and is the evolutionary replacement for the parallel ATA interface.
The enhanced feature set of SATA includes improved cabling dimension and smaller plug form factor, faster data rate, and hot plugging.
Highlights
- Compliant with Serial ATA 1.0a and II specifications
- Supports 1.5 Gbps and 3.0 Gbps
- Supports Native Command Queuing (NCQ)
- Integrated SATA link layer and transport layer logic
- "Lightweight" AHB slave interface
- Supports PIO, first party and legacy DMA modes
- Supports legacy command queuing
- Supports ATA and ATAPI master-only emulation mode (i.e., register and command compatible with these standards)
- Power-down mode
- Data scrambling
- CRC computation
- Configurable PHY/Link Interface - 8b/10b encoding (optional)
- OOB detection/generation (optional)
- Data alignment (optional) - Elasticity buffers (optional)
- Synchronous or asynchronous read-port RAM interface support
- Smaller FIFOs (< 256 deep) can be implemented using internal registers
- FIFO sizes are configurable and set by user
- Automatic data flow control
- Far end loop-back re-timed
- Highly parameterized - FIFO depth - Memory Select-external or internal - Memory Mode-asynchronous or synchronous
- PHY data bus width
- Asynchronous receive clock support
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