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Overview
Synopsys' DesignWare® PCI Express PHY is a complete mixed-signal semiconductor intellectual property (IP) solution, designed for integration in root complex, endpoint, dual-mode, and switch applications.
The PCI Express PHY includes all of the required logical and physical design files needed for integration in a System-on-Chip (SoC) design.
Industry standard PIPE interface and validated compatibility with the DesignWare PCI Express Endpoint Digital Controller enable easy integration of the PCI Express solution into a variety of applications,
in high end compute, server, data center, consumer and graphics markets. The PCI Express PHY integrates high-speed mixed-signal custom CMOS circuitry compliant with the PCI Express 1.1 base specification and the PIPE interface standard.
While extremely low in power consumption and area requirements, the DesignWare PCI Express PHY substantially exceeds the electrical specifications in such key performance areas as jitter and receive sensitivity.
Synopsys provides designers with a complete, silicon-proven PCI Express 1.1 IP solution, including digital controllers, PHY and verification IP from a single vendor.
Accessing all the IP from one provider allows designers to lower the risk and cost of integrating the 2.5 Gbps PCI Express interface into their high performance SoC designs.
The PCI Express standard builds upon PCI and PCI-X® technologies to provide increased bandwidth and capabilities while reducing board costs, without requiring changes to existing PCI software.
With over 10 years of PCI leadership, Synopsys is the #1 supplier of PCI cores providing designers with the most rigorously tested, silicon-proven IP in the industry.
Highlights
- Supports a wide range of configurations including 1.0v & 1.2v core supplies and 2.5v & 3.3v I/O supplies
- Supports a wide range of PCI Express bus widths (up to x16 support)
- Fully compliant with PCI Express 1.0a and 1.0a Errata and PIPE interface to ensure interoperability and ease of integration with higher protocol levels
- Supports all power-down states for highly efficient operation
- Full support for beaconing, receiver detection and electrical idle
- Reliable link operation across channel manufacturing operation (BER<10-18)
 DesignWare PHY/Serdes Technology Backgrounder
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