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Overview
The DesignWare® Endpoint (EP) PCI Express™ Core is configurable and scalable to meet multiple endpoint application requirements.
The enhanced capabilities of the DesignWare EP core allow for optimal on-chip memory size and utilization, significant power savings and low latency.
The core implements most advanced capabilities of PCI Express such as active state power management, advanced error reporting, multiple functions, multiple virtual channels, and End-to-End CRC.
The application interface directly supports multiple clients and offers maximum flexibility for end-use applications.
The synthesizable core integrates quickly and easily into SoC designs with a user-friendly application interface and conservative timing suitable for a wide range of ASIC and FPGA technologies.
The core is available in your choice of datapath widths, PIPE interface widths, and operating frequencies for optimization of size, power, and throughput.
DesignWare PCI Express cores are fully compliant with the PCI Express Base Specification 1.1/2.0 and are used to power the industry's PCI Express compliance testing at PCI-SIG Compliance Workshops.
Applications
The DesignWare Endpoint core supports a wide variety of PCI Express 1.1/2.0 Endpoint applications:
- Data Communications
- Telecommunications
- Storage Area Networks
- LAN Interfaces
- Graphics Devices
- Wireless Devices
- Other I/O applications
Highlights
- Designed according to the 1.1/2.0 PCI Express specifications, including the latest errata
- Architecture supports x1, x2, x4, x8, and x16 2.5/5.0Gbps lane configurations
- Available in 32, 64, or 128 bit datapath widths
- Modular design: base core with additional support modules
- 125MHz/250MHz/500MHz operation
- Type 0 configuration space
- Supports PIPE PHY 1.86 interface definition including variable clock and variable data
- Ultra low transmit and receive latency
- Configurable retry buffer size
- Configurable outstanding request: supports up to 32 lookup entries without RAM, beyond 32 entries with RAM
- Very high accessible bandwidth
- Lane reversal and polarity inversion (TX/RX)
- Configurable multi-VCs/multi traffic class support
- Configurable multi-function support
- Packet sizes: configurable max payload size (128B to 4KB) and max request size up to 4KB
- Supports bypass, cut-through, and store-and-forward request queues with PCIe credit management, as well as configurable for infinite credits for all type of traffic
- Configurable ECRC generation and check
- Complete Link Training (LTSSM)
- Beacon and wake-up mechanism
- Full PCI-PM software and ASPM
- Full Advanced PCI Express Error Reporting
- All in-band messages supported for EP
- Legacy, MSI, and MSI-X interrupt support
- Configurable EP filtering rules for posted, non-posted and completion traffic
- Configurable BAR filtering, IO filtering, configuration filtering and completion lookup/timeout for EP
- Support for three application clients
- In-band and out-of-band access to configuration space registers and external user application registers with local bus controller
- Supports expansion ROM
- Optional checking
- VPD capability register support
- Device serial number capability
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