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Overview
The DesignWare® PCI Express® to AMBA™ 3 AXI™ Bridge Core (PCIe®-AXI Bridge) enables designers who use the
AMBA 3 AXI on-chip bus to easily add PCI Express external connectivity to their AMBA 3 AXI based System-on-Chip (SoC) devices.
The PCIe-AXI Bridge is designed to work in conjunction with the complete portfolio of silicon proven DesignWare Cores for PCI Express 1.1 and 2.0 (Gen II), including Endpoint, Root Complex, Switch, Bridge and Dual Mode.
The PCIe-AXI Bridge is configurable and scalable to meet multiple application requirements of today's demanding high-bandwidth, low latency designs.
The PCIe-AXI Bridge handles all the issues needed to successfully connect these two protocols together.
The PCIe-AXI Bridge provides the standard AMBA AXI interfaces and the bridging logic that maps the connection between the SoCs AXI interconnect and the native interface of the DesignWare PCI Express portfolio of cores.
The PCIe-AXI Bridge optionally supports up to three AXI interfaces, one for an AXI master, one for an AXI slave, and one for Data Bus Interface (DBI) access to the PCI Express core.
The AXI Master and Slave interfaces of the PCIe-AXI Bridge enable the PCI Express interface to be an AXI slave or an AXI master.
The master and slave interfaces handle AXI protocol, internal slave and master control for generic request and responses, a packet composer, and a packet decomposer.
The SoC can read from, or write to registers within the DesignWare PCI Express
core through a slave DBI interface. The AXI channel read/write address directly control the address mapped inside the PCI Express cores' CDM register map.
The PCIe-AXI Bridge master interface handles all types of inbound transactions received by the PCI Express interface to the SoC.
This enables a remote PCI Express device connected on the link to send a transaction through the PCIe-AXI Bridge from a PCI Express device to any AXI slave within the SoC.
The PCIe-AXI Bridge slave interface handles all types of outbound transactions from the SoC AXI interconnect that are targeted to a remote PCI Express device connected to the PCI Express bus.
Applications
The DesignWare PCI Express to AMBA 3 AXI Bridge supports a wide variety of PCI Express applications:
- Data Communications
- Telecommunications
- Storage Area Networks
- LAN Interfaces
- Graphics Devices
- Wireless Devices
- Other I/O applications
Highlights
- AXI Master and slave interfaces for inbound and outbound PCI Express requests
- Supports full PCI Express configuration, I/O requests, traffic class (EP, TD, etc.) through PCIe-AXI
- AXI Slave interface for PCI Express core CDM register access through the PCI Express core's DBI interface
- Independent configuration of bus width for PCI Express core data bus, AXI master bus and AXI slave bus
- Programmable buffer sizes for AXI master and slave requests and response queuing
- Independent programmable clock rates for the PCI Express core, the AXI master bus, the AXI slave bus and the AXI slave DBI bus
- Programmable AXI master and slave address widths, data bus widths, and ID bus widths
- Programmable maximum number of inbound and outbound read requests for AXI
- All burst-sizes supported for both AXI master and slave interfaces
- Programmable burst lengths to support 4K read/write burst over AXI master and slave interfaces
- Supports unaligned AXI transfers using WSTRB and RTSRB for both AXI master and slave interfaces
- Supports independent maximum read request and transfer sizes between the AXI and PCI Express (transfers can be split into multiple transfers)
- Supports response AXI slave request gathering from split PCI Express completions
- Supports response AXI master request gathering from multiple AXI responses
- Supports out-of-order transactions for transactions with unique IDs
- Supports Interrupt and Message handling
- Supports response error mapping between PCI Express errors (UR, CA, CRS, poisoned, and ECRC error) and AXI slave response errors (SLVERR and DECERR)
- Supports response error mapping between PCI Express errors (UR, CA, CRS, poisoned, and ECRC error) and AXI master response error (DECERR_W and DECERR_R)
- Support for byte parity check for the address and data buses though the PCIe-AXI Bridge
- PCIe-AXI Bridge handles completion time outs
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