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Overview
Synopsys' DesignWare® JPEG CODEC is part of an SoC-based multimedia solution that enables fast and simple image compression and decompression.
The CODEC encodes and decodes still or motion image data of up to four-color components, according to the JPEG baseline algorithm (as specified in the ISO/IEC 10918-1 standard).
The design's simplicity allows for easy SoC integration, high-speed operation, and suitability for multimedia and color printing applications.
Highlights
- 100% baseline ISO/IEC 10918-1 JPEG-compliant
- Verified in hardware
- 8-bit channel pixel depths
- Up to four programmable quantization tables
- Single-clock Huffman coding and decoding
- Fully programmable Huffman tables (two AC and two DC)
- Fully programmable Minimum Coded Unit (MCU)
- Encoding/decoding support (non-simultaneous)
- Single-clock per pixel encoding and decoding
- Support for up to four channels of component color
- Four-channel interface
- Simple external interface
- Low gate count-total gate count is 35K gates
- Stallable design
- Hardware support for restart marker insertion
- Support for single, grayscale components
- Internal register interface
- Fully synchronous design
- Available as fully functional and synthesizable Verilog
- Includes testbench
- Individual Encoder and Decoder products are available from Synopsys
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